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| author | Stefan Agner <stefan.agner@toradex.com> | 2015-10-23 16:02:10 -0700 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2015-10-23 16:02:10 -0700 |
| commit | 091ab2e4b26453de4b3fe1a67d3e366ce36bfe49 (patch) | |
| tree | 8f27e2958fbca3e8ebba6928614e06c38940cf44 /arch/arm/boot | |
| parent | 0df341edfa5e7c119523a0c30146e88106f88b43 (diff) | |
ARM: dts: vf610-colibri: use reset values for L2 cache latencies
The values which we used so far used to be a mix between the values
of the Linux 3.0 based BSP and the values used in the upstream kernel
tree. The origin of both value is likely not related to Vybrid and
just wrong (see the corsponding Freescale Community thread). The
reset values seem to be the better bet. Performance mesurement did
not show any impact or at best very marginal improvement.
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/vf610-colibri.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi index 2da52bbf5ce6..4c94254e4a60 100644 --- a/arch/arm/boot/dts/vf610-colibri.dtsi +++ b/arch/arm/boot/dts/vf610-colibri.dtsi @@ -56,8 +56,8 @@ }; &L2 { - arm,data-latency = <2 1 2>; - arm,tag-latency = <3 2 3>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; }; &iomuxc { |