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| author | Stefan Agner <stefan.agner@toradex.com> | 2016-08-10 14:45:12 +0530 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2016-09-29 13:56:30 -0700 |
| commit | fdbb13c837ef426cc81634ea182e9683b4989dd6 (patch) | |
| tree | 825b17c69544fec3c5bc8bddbc7f7ada4a3b1e1a /arch/arm/boot | |
| parent | 91294bef8e9e3a3069f7ac3fc9fdb4a4992fc39a (diff) | |
ARM: dts: vfxxx: Add CPU2CPU interrupts for MSCM module
Add CPU2CPU interrupts for MSCM module.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/vfxxx.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 3c64f11fbcd8..c802d1044ac2 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -119,10 +119,22 @@ mscm_ir: interrupt-controller@40001800 { compatible = "fsl,vf610-mscm-ir"; + #address-cells = <1>; + #size-cells = <1>; reg = <0x40001800 0x400>; fsl,cpucfg = <&mscm_cpucfg>; interrupt-controller; #interrupt-cells = <2>; + + cpu2cpu@40001800 { + reg = <0x40001800 0x40>; + interrupt-parent = <&mscm_ir>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <1 IRQ_TYPE_LEVEL_HIGH>, + <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1", "int2", "int3"; + }; }; edma0: dma-controller@40018000 { |