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| author | Stefan Agner <stefan.agner@toradex.com> | 2016-01-22 15:33:21 -0800 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-01-10 23:13:21 +0100 |
| commit | 0d85191ac6663ea3e2ff84d96f20c62144549f27 (patch) | |
| tree | ea80414503ee7d6acb8556ac017714de082323cc /arch/arm/configs/apalis_imx6_defconfig | |
| parent | 8ddc702c57a79cf0f4e8334ba6a593b472cfd44a (diff) | |
tty: serial: imx: disable DCD and RI interrupts
If the UART is in DTE mode, the signals DCD and RI are inputs. In
this case, the control bits in UCR3_DCD and UCR3_RI control the
interrupt of those two inputs. The two bits are 1 on reset, hence
leading to an interrupt if one of those signal changes... However,
as of now the interrupt handler does not handle these interrupts,
leading to a interrupt strom.
Solve the issue by explicitly disabling the two interrupts during
initialization.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 2d027fec8264daa4cda1bcc81cabb91bd97cde0b)
Diffstat (limited to 'arch/arm/configs/apalis_imx6_defconfig')
0 files changed, 0 insertions, 0 deletions