diff options
| author | Pawel Moll <pawel.moll@arm.com> | 2011-01-25 15:53:03 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-01-25 16:18:33 +0000 |
| commit | baaece224570a935210a59257b5d9073e99843ea (patch) | |
| tree | 1b0af1903ce4a58122473cca2d128ae1f56726c0 /arch/arm/include/asm/hardware | |
| parent | e5310f611d17ed4e92e0d4e46fd9f6fb40e66df3 (diff) | |
ARM: 6635/2: Configure reference clock for Versatile Express timers
Timers on Versatile Express mainboard are used as system clock/event
sources. Driver assumes that they are clocked with 1MHz signal.
Old V2M firmware apparently configured it by default, but on newer
boards one can observe that "sleep 1" command takes over 30 seconds
to finish, as the timers are fed with 32kHz instead...
This patch performs required magic and also removes code clearing
timer's control registers, as exactly the same operations are
performed by the timer driver few jiffies later.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/hardware')
| -rw-r--r-- | arch/arm/include/asm/hardware/sp810.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h index a101f10bb5b1..721847dc68ab 100644 --- a/arch/arm/include/asm/hardware/sp810.h +++ b/arch/arm/include/asm/hardware/sp810.h @@ -50,6 +50,12 @@ #define SCPCELLID2 0xFF8 #define SCPCELLID3 0xFFC +#define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15) +#define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15) + +#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17) +#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17) + static inline void sysctl_soft_reset(void __iomem *base) { /* writing any value to SCSYSSTAT reg will reset system */ |