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| author | Grant Likely <grant.likely@secretlab.ca> | 2011-05-20 00:43:00 -0600 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2011-05-20 00:43:00 -0600 |
| commit | 78fab4c04c76b8c9327541bd270f82b85b42bbf7 (patch) | |
| tree | b43006348a1ac15c28e6791d08646809761a2a4a /arch/arm/include/asm/system.h | |
| parent | 3b8a4dd3ebfcc647260ad5c39ef4f73eb3a6b155 (diff) | |
| parent | 61c4f2c81c61f73549928dfd9f3e8f26aa36a8cf (diff) | |
Merge commit 'v2.6.39' into spi/next
Diffstat (limited to 'arch/arm/include/asm/system.h')
| -rw-r--r-- | arch/arm/include/asm/system.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9a87823642d0..832888d0c20c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -159,7 +159,7 @@ extern unsigned int user_debug; #include <mach/barriers.h> #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) #define mb() do { dsb(); outer_sync(); } while (0) -#define rmb() dmb() +#define rmb() dsb() #define wmb() mb() #else #include <asm/memory.h> @@ -249,7 +249,7 @@ do { \ * cache totally. This means that the cache becomes inconsistent, and, * since we use normal loads/stores as well, this is really bad. * Typically, this causes oopsen in filp_close, but could have other, - * more disasterous effects. There are two work-arounds: + * more disastrous effects. There are two work-arounds: * 1. Disable interrupts and emulate the atomic swap * 2. Clean the cache, perform atomic swap, flush the cache * |