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authorColin Cross <ccross@android.com>2011-04-07 14:47:45 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:37:03 -0800
commit8044175af9e16ae5f315029e629f84f88e78d1d4 (patch)
tree2974dedc8f619dfd81c6be0b08fccfa2b65ecb8e /arch/arm/include
parenta6fe57bb9aa543f85754470f0d4d7636933bde69 (diff)
[ARM] mm: add memory type for inner-writeback
For streaming-style operations (e.g., software rendering of graphics surfaces shared with non-coherent DMA devices), the cost of performing L2 cache maintenance can exceed the benefit of having the larger cache (this is particularly true for OUTER_CACHE configurations like the ARM PL2x0). This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) in the tex remapping tables as an inner-writeback-write-allocate, outer non-cacheable memory type, so that this mapping will be available to clients which will benefit from the reduced L2 maintenance. Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906 Signed-off-by: Gary King <gking@nvidia.com> Conflicts: arch/arm/include/asm/pgtable.h arch/arm/mm/proc-v7.S
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/pgtable.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 5750704e0271..6e68977529c0 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -189,6 +189,7 @@ extern void __pgd_error(const char *file, int line, pgd_t);
#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
+#define L_PTE_MT_INNER_WB (_AT(pteval_t, 0x05) << 2) /* 0101 (armv6, armv7) */
#ifndef __ASSEMBLY__
@@ -244,6 +245,9 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
#endif
+#define pgprot_inner_writeback(prot) \
+ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_INNER_WB)
+
#endif /* __ASSEMBLY__ */
/*