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authorScott Williams <scwilliams@nvidia.com>2010-12-20 15:40:35 -0800
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:46:36 -0800
commite0f9726d23b19f0a27c67f02aa11e81ced2c0b7e (patch)
tree6d6d736be282ae254ab0403552c8955084252b66 /arch/arm/kernel
parent45c89e9b030d76f18d0477fa0f0778f82e59953c (diff)
ARM: Disallow DCC writes from secondary processors
An attempt to access the DCC console from secondary processors will result in those processors hanging because the JTAG debugger can only communicate with one core at a time. Allow DCC output only from CPU 0. Useful for bringup, not necessarily for upstream Original-Change-Id: I9118555438f5b72b16a2dfccd5b6f98860505d6d Reviewed-on: http://git-master/r/13876 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I36bb0351e0899f4ad8732fe784623f7eea57dff5 Rebase-Id: R32383c2b0268f8111444b7b75c4fa3d2b3ddbaef
Diffstat (limited to 'arch/arm/kernel')
-rw-r--r--arch/arm/kernel/debug.S10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index bcd66e00bdbe..9126592867f4 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -154,6 +154,11 @@ ENDPROC(printhex2)
.ltorg
ENTRY(printascii)
+#if defined(CONFIG_DEBUG_ICEDCC) && defined(CONFIG_SMP)
+ mrc p15, 0, r3, c0, c0, 5
+ ands r3, r3, #3
+ movne pc, lr
+#endif
addruart_current r3, r1, r2
b 2f
1: waituart r2, r3
@@ -170,6 +175,11 @@ ENTRY(printascii)
ENDPROC(printascii)
ENTRY(printch)
+#if defined(CONFIG_DEBUG_ICEDCC) && defined(CONFIG_SMP)
+ mrc p15, 0, r3, c0, c0, 5
+ ands r3, r3, #3
+ movne pc, lr
+#endif
addruart_current r3, r1, r2
mov r1, r0
mov r0, #0