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authorNicolas Pitre <nico@cam.org>2008-03-31 12:38:31 -0400
committerLennert Buytenhek <buytenh@marvell.com>2008-06-22 22:44:38 +0200
commit2239aff6ab2b95af1f628eee7a809f21c41605b3 (patch)
treefd940074a312d252976da05f7e4457c446e14027 /arch/arm/lib/memmove.S
parent4c4925c1f4ccd72002957c3e73b4f117f2bcf712 (diff)
[ARM] cache align destination pointer when copying memory for some processors
The implementation for memory copy functions on ARM had a (disabled) provision for aligning the source pointer before loading registers with data. Turns out that aligning the _destination_ pointer is much more useful, as the read side is already sufficiently helped with the use of preload. So this changes the definition of the CALGN() macro to target the destination pointer instead, and turns it on for Feroceon processors where the gain is very noticeable. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch/arm/lib/memmove.S')
-rw-r--r--arch/arm/lib/memmove.S12
1 files changed, 2 insertions, 10 deletions
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index 018522c3ff26..2e301b7bd8f1 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -13,14 +13,6 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
-/*
- * This can be used to enable code to cacheline align the source pointer.
- * Experiments on tested architectures (StrongARM and XScale) didn't show
- * this a worthwhile thing to do. That might be different in the future.
- */
-//#define CALGN(code...) code
-#define CALGN(code...)
-
.text
/*
@@ -55,7 +47,7 @@ ENTRY(memmove)
stmfd sp!, {r5 - r8}
blt 5f
- CALGN( ands ip, r1, #31 )
+ CALGN( ands ip, r0, #31 )
CALGN( sbcnes r4, ip, r2 ) @ C is always set here
CALGN( bcs 2f )
CALGN( adr r4, 6f )
@@ -139,7 +131,7 @@ ENTRY(memmove)
subs r2, r2, #28
blt 14f
- CALGN( ands ip, r1, #31 )
+ CALGN( ands ip, r0, #31 )
CALGN( sbcnes r4, ip, r2 ) @ C is always set here
CALGN( subcc r2, r2, ip )
CALGN( bcc 15f )