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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2015-03-12 10:06:30 +0200
committerSekhar Nori <nsekhar@ti.com>2015-03-18 17:17:36 +0530
commitb38434145b341c148b8d98cfbfc1e87bb4d9e2d9 (patch)
treee67a0ef7589fb46e0a9f7d8ab915144dd6102eb0 /arch/arm/mach-davinci/dm646x.c
parent256b20a54a13962a9fcffabbc08903301fa4c259 (diff)
ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x
McASP1 TX interrupt is 30, not 32 on DM646x DMSoC. While at it remove the bogus AEMIF interrupt entry from dm646x_default_priorities[]. AEMIF interrupt on DM6467 is 60 not 30 and the entry for the correct interrupt number is already present in the same table. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> [nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'arch/arm/mach-davinci/dm646x.c')
-rw-r--r--arch/arm/mach-davinci/dm646x.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index d2a2619aee81..58769eddd3c3 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
[IRQ_DM646X_EMACMISCINT] = 7,
[IRQ_DM646X_MCASP0TXINT] = 7,
[IRQ_DM646X_MCASP0RXINT] = 7,
- [IRQ_AEMIFINT] = 7,
[IRQ_DM646X_RESERVED_3] = 7,
[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
[IRQ_TINT0_TINT34] = 7, /* clocksource */