diff options
| author | Anson Huang <b20788@freescale.com> | 2015-09-03 01:05:48 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2015-09-03 01:34:41 +0800 |
| commit | e4d0573ae88aa7e1216fa6dbc0fcbeb61cc70a49 (patch) | |
| tree | 89f40ee835ffbca9ae12898f867b2b41f333fa2e /arch/arm/mach-imx/anatop.c | |
| parent | d9dd229076c09173b674becda8b57b94c61089bb (diff) | |
MLK-11492 ARM: imx: keep weak 2p5 on for USB vbus wakeuprel_imx_3.14.38_6ul_9x9_patch
Since i.MX6SX, if USB vbus wake up is enabled, weak 2P5
needs to be on even if the DRAM is LPDDR2, previously, we need
to set stop_mode_config to keep 2P5 on, so enter DSM,
if USB vbus wakeup is enabled, we need to keep weak 2P5 on.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/anatop.c')
| -rw-r--r-- | arch/arm/mach-imx/anatop.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 22c30081f020..9770a5f17d89 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -137,7 +137,8 @@ void imx_anatop_pre_suspend(void) if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) imx_anatop_disable_pu(true); - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) && + !imx_gpc_usb_wakeup_enabled()) imx_anatop_enable_2p5_pulldown(true); else imx_anatop_enable_weak2p5(true); @@ -164,7 +165,8 @@ void imx_anatop_post_resume(void) if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) imx_anatop_disable_pu(false); - if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) && + !imx_gpc_usb_wakeup_enabled()) imx_anatop_enable_2p5_pulldown(false); else imx_anatop_enable_weak2p5(false); |