diff options
| author | Anson Huang <b20788@freescale.com> | 2014-10-09 17:50:46 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-01-15 21:18:20 -0600 |
| commit | 19a30efd1ad7aa9d74684d57120a6108e41c98ed (patch) | |
| tree | 0ad6ac9fd79f1afc9aaf915ac9800464a5b89750 /arch/arm/mach-imx/clk-imx6q.c | |
| parent | 9d08142952fc84a5802fc06236f1d046fe8054a4 (diff) | |
MLK-9669-1 arm: imx: skip system bus related clks parent switch check
Those system bus related mux only can be switched by busfreq driver,
and in busfreq asm code, it already follow the flow that hardware design
require, so no need to do flow check for these clk mux:
i.MX6Q/DL: periph_clk2_sel and pre_periph_clk_sel;
i.MX6SL: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel
i.MX6SX: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 9633423e7de2..314bdb15e00d 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -268,9 +268,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* name reg shift width parent_names num_parents */ clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); - clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); clk[IMX6QDL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux_glitchless("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels)); |