diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2015-08-24 13:56:17 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-01-10 23:11:48 +0100 |
| commit | 691204a1e59f6427688adba36797478c44c1dcca (patch) | |
| tree | f520c9e6a400b54963c3aa877d077fff40a04b76 /arch/arm/mach-imx/clk-imx6q.c | |
| parent | bea05755680df306e93e5a13f730fd1db203f947 (diff) | |
clk-imx6q.c: set eth phy clock dependent on RMII/RGMII
Evaluate the device tree to find out about the used phy mode rather than
using a hardcoded value of 125MHz valid for RGMII only.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
(cherry picked from commit 97f5120f2330550d500231b7bf27e7433fd31508)
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index ad0897ac5832..bfd7681aad29 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -19,6 +19,8 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/of_net.h> +#include <linux/phy.h> #include <dt-bindings/clock/imx6qdl-clock.h> #include "clk.h" @@ -350,7 +352,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i; + int i, phy_mode; u32 val; clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -897,8 +899,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); } - /*Set enet_ref clock to 125M to supply for RGMII tx_clk */ - clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000); + /*Set enet_ref clock to 125M to supply for RGMII tx_clk or to 50M for RMII */ + phy_mode = PHY_INTERFACE_MODE_RGMII; + np = of_find_node_by_name(NULL, "ethernet"); + if (of_device_is_available(np)) + phy_mode = of_get_phy_mode(np); + else { + phy_mode = PHY_INTERFACE_MODE_RGMII; + } + of_node_put(np); + clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], phy_mode != PHY_INTERFACE_MODE_RMII ? 125000000 : 50000000); #ifdef CONFIG_MX6_VPU_352M /* |