diff options
| author | Gao Pan <b54642@freescale.com> | 2015-12-14 21:43:55 +0800 |
|---|---|---|
| committer | Adrian Alonso <adrian.alonso@nxp.com> | 2016-02-03 17:34:11 -0600 |
| commit | bbb86e41c9ab23eb8c128e926542117bec9ddc45 (patch) | |
| tree | a63f256b6c3f672be4de73f9fab87c49d8c6a9ec /arch/arm/mach-imx/clk-imx6q.c | |
| parent | 3593daea2b4f1cc066b062e5077569c63f309fd2 (diff) | |
MLK-12013 arm: imx: set eim_slow clk to 132Mhz only for MXC_CPU_IMX6Q
A patch(set imx6qp eim_slow to 132Mh) was pushed to eliminate
the weim nor read performance drop cause by the IP difference
between imx6q & imx6qp.
However, the patch impacted the performance of imx6dl-ard.
In succession, AXI clk is set to 270M which exceeds the max
value(264M).
This patch sets eim_slow to 132M only for MXC_CPU_IMX6Q. So
the performance difference between imx6q & imx6qp decreases
while no impact for imx6dl-ard.
please see the following summary of weim nor read performance.
clk(performance) 6q-sabreauto 6qp-sabreauto 6dl-ard
imx_3.10 132M(18.9MB/s) —— 135M(19.1MB/s)
imx_3.14.y 132M(18.9MB/s) 132M(16.8MB/s) 135M(19.1MB/s)
Signed-off-by: Gao Pan <b54642@freescale.com>
(cherry picked from commit f19e9899eacddb5343e7a7d476a500cd4551dffe)
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 7ba7bc1e8200..f45de65aa673 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -810,11 +810,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) } else if (cpu_is_imx6q()) { imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]); imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]); + /* set eim_slow to 132Mhz */ + imx_clk_set_rate(clk[IMX6QDL_CLK_EIM_SLOW], 132000000); } - imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_ALT_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); - imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_SEL], clk[IMX6QDL_CLK_AXI_ALT_SEL]); - /* * The gpmi needs 100MHz frequency in the EDO/Sync mode, * We can not get the 100MHz from the pll2_pfd0_352m. @@ -868,9 +867,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if (IS_ENABLED(CONFIG_PCI_IMX6)) imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); - /* set eim_slow to 135Mhz */ - imx_clk_set_rate(clk[IMX6QDL_CLK_EIM_SLOW], 135000000); - /* * Enable clocks only after both parent and rate are all initialized * as needed |