diff options
author | Jason Liu <r64343@freescale.com> | 2015-01-06 11:23:59 +0800 |
---|---|---|
committer | Nitin Garg <nitin.garg@freescale.com> | 2015-01-15 21:20:03 -0600 |
commit | 1cffe65f3021e77cc4070e2be68fc1695b480289 (patch) | |
tree | 11da9890591d4a9028f91fb4f9f8ae1151887eb2 /arch/arm/mach-imx/clk-imx6sx.c | |
parent | 905ab1d1aea28b415ae98e205b6299f0cd2c8798 (diff) |
Need gate the QSPI2 and GPMI_IO clock during clock init
QSPI2/GPMI_IO share the same clock source but with the
different gate, need explicitely gate the QSPI2 & GPMI_IO
during the clock init phase according to the SOC design.
The topo of the clock for the GPMI_IO and NAND as below:
mux --> pre divider --> post divider --gate-- >GPMI_IO
|-gate-- >QSPI2
(Note: i.MX6SX:GPMI_NAND and GSPI2 is PINMUX conflicts.)
The SOC design spec required that if change the parent clock
of the GPMI_IO or QSPI2, need gate the GPMI_IO and QSPI2 first
otherwise, there will have some glitch which cause the divider
malfunciton. Thus, we need explicitely gate QSPI2 & GPMI_IO at
the clock initialization phase and then later on common clock
framework will gurantee that each time, the parent clock rate
changes after the child clock is disabled(gated).
Signed-off-by: Jason Liu <r64343@freescale.com>
(cherry picked from commit 110d63a5886e065e77a69f816216af044c096a44)
Conflicts:
arch/arm/mach-imx/clk-imx6sx.c
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6sx.c')
-rw-r--r-- | arch/arm/mach-imx/clk-imx6sx.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index ba112f3c6f30..6b3816edd352 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -24,6 +24,7 @@ #include "clk.h" #include "common.h" +#define CCM_CCGR_OFFSET(index) (index * 2) #define CCDR 0x4 #define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16) @@ -561,6 +562,14 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) if (IS_ERR(clks[i])) pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); + /* + * QSPI2/GPMI_IO share the same clock source but with the + * different gate, need explicitely gate the QSPI2 & GPMI_IO + * during the clock init phase according to the SOC design. + */ + writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78); + writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78); + clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |