diff options
| author | Adrian Alonso <adrian.alonso@nxp.com> | 2016-02-18 13:36:36 -0600 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:24:30 +0800 |
| commit | 3c9aeecae2fb711c3e2cfd623e30538ec7e9b533 (patch) | |
| tree | a93db29017022b8a25ac6559adeeb493f5caaf23 /arch/arm/mach-imx/ddr3_freq_imx6sx.S | |
| parent | 3b639bbaad32d80bf44bacad5b6f6383e63d01d2 (diff) | |
MLK-12415: ARM: imx: imx6q: ddr3 adjust read/write latency from DCD
Adjust high frequence (528M) read/write additional latency settings
from target board initial configuration; Save/restore MMDC_MDMISC
from DCD settings.
Remove hardcodded value to issue a ZQ calibration command.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
(Cherry picked from commit 1036293d72173ef9051ec23babfd4d7f13db4f58)
Diffstat (limited to 'arch/arm/mach-imx/ddr3_freq_imx6sx.S')
| -rw-r--r-- | arch/arm/mach-imx/ddr3_freq_imx6sx.S | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/ddr3_freq_imx6sx.S b/arch/arm/mach-imx/ddr3_freq_imx6sx.S index 4dc89b9c3744..9846c05f4541 100644 --- a/arch/arm/mach-imx/ddr3_freq_imx6sx.S +++ b/arch/arm/mach-imx/ddr3_freq_imx6sx.S @@ -401,7 +401,11 @@ poll_dvfs_clear_1: orr r8, r8, #0x4 str r8, [r4, #MMDC0_MDCF1] - ldr r8, =0x00091680 + ldr r8, [r4, #MMDC0_MDMISC] + bic r8, r8, #(0x3 << 16) /* walat = 0x1 */ + orr r8, r8, #(0x1 << 16) + bic r8, r8, #(0x7 << 6) /* ralat = 0x2 */ + orr r8, r8, #(0x2 << 6) str r8, [r4, #MMDC0_MDMISC] /* enable dqs pull down in the IOMUX. */ @@ -506,7 +510,9 @@ poll_dvfs_clear_2: cmp r2, #0 beq update_calibration_only - ldr r8, =0xa5390003 + /* issue zq calibration command */ + ldr r8, [r4, #MMDC0_MPZQHWCTRL] + orr r8, r8, #0x3 str r8, [r4, #MMDC0_MPZQHWCTRL] /* enable DQS gating. */ @@ -551,10 +557,6 @@ update_iomux1: str r11, [r4, r10] add r1, r1, #8 - /* update MISC register: WALAT, RALAT */ - ldr r8, =0x00081740 - str r8, [r4, #MMDC0_MDMISC] - /* configure ddr devices to dll on, odt. */ ldr r8, =0x00028031 str r8, [r4, #MMDC0_MDSCR] |