ENGR00331269-2 ARM: imx: add A9-M4 clk/power management for i.mx6sx

As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:

1. clk management: for every clk node, only when both A9 and
   M4 do NOT need it, then we can disable it from hardware;
2. power management: only when both A9 and M4 agree to enter
   low power mode, then system can enter it.

Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.

For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.

For power management, M4 is treated as a high speed device
in A9 side, M4 is booting up with 227MHz by default, only
when M4 freq drop to below than 24MHz, then A9 is able to
enter low bus mode and low power idle mode. Everytime A9
is trying to adjust bus freq, it will request M4 to stay
at wfi, and once bus freq scaling is done, A9 will send
message to wake up M4 to continue, this is because M4 can
NOT access DDR or other important bus during bus freq scaling.
Whenever M4 wants high bus freq, it can send message to A9 to
increase bus freq, All these communications are done by MU
module.

For further use case implementation, we can define new protocol
to achieve, everytime MU receives a message, it will trigger
a thread to handle this request, A9 can response according
to the message.

Signed-off-by: Anson Huang <b20788@freescale.com>

1 files changed, 13 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 04826075a7de..688d5771a135 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -53,6 +53,9 @@
 #define PGC_PCIE_PHY_PDN_EN		0x1
 #define GPC_CNTR_PU_UP_REQ_SHIFT	0x1
 #define GPC_CNTR_PU_DOWN_REQ_SHIFT	0x0
+#define GPC_M4_LPSR			0x2c
+#define GPC_M4_LPSR_M4_SLEEPING_SHIFT	4
+#define GPC_M4_LPSR_M4_SLEEPING_MASK	0x1
 
 #define IMR_NUM			4
 
@@ -149,6 +152,16 @@ static void imx_gpc_dispmix_off(void)
 	}
 }
 
+unsigned int imx_gpc_is_m4_sleeping(void)
+{
+	if (readl_relaxed(gpc_base + GPC_M4_LPSR) &
+		(GPC_M4_LPSR_M4_SLEEPING_MASK <<
+		GPC_M4_LPSR_M4_SLEEPING_SHIFT))
+		return 1;
+
+	return 0;
+}
+
 unsigned int imx_gpc_is_mf_mix_off(void)
 {
 	return readl_relaxed(gpc_base + GPC_PGC_MF_PDN);