diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-01-14 19:13:34 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:24:11 +0800 |
| commit | ade976f301face39dab478f71ee826efa2fdaa6f (patch) | |
| tree | a08c599c7213e897a71aacd4ea4eec7ec0ed6bed /arch/arm/mach-imx/lpddr3_freq_imx.S | |
| parent | 90eaa567809563d39e567663ac14f0606a22507a (diff) | |
MLK-12136-3 ARM: imx: adjust ddr frequency scale flow on i.MX7D TO1.1
i.MX7D TO1.1 updates the DDR script, ddr frequency scale flow
should be updated accordingly.
Add runtime revision check to support both TO1.0 and TO1.1.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/lpddr3_freq_imx.S')
| -rw-r--r-- | arch/arm/mach-imx/lpddr3_freq_imx.S | 40 |
1 files changed, 36 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/lpddr3_freq_imx.S b/arch/arm/mach-imx/lpddr3_freq_imx.S index 9357627d8c57..f9951c96d869 100644 --- a/arch/arm/mach-imx/lpddr3_freq_imx.S +++ b/arch/arm/mach-imx/lpddr3_freq_imx.S @@ -38,10 +38,13 @@ #define DDRPHY_OFFSETW_CON1 0x34 #define DDRPHY_OFFSETW_CON2 0x38 #define DDRPHY_RFSHTMG 0x64 +#define DDRPHY_CA_WLDSKEW_CON0 0x6c #define DDRPHY_CA_DSKEW_CON0 0x7c #define DDRPHY_CA_DSKEW_CON1 0x80 #define DDRPHY_CA_DSKEW_CON2 0x84 +#define ANADIG_DIGPROG 0x800 + .align 3 .macro ddrc_prepare @@ -179,11 +182,25 @@ ldr r7, =0x7f str r7, [r5, #DDRPHY_OFFSETW_CON2] + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x10 + beq 11f + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + ldr r7, =0x60606060 str r7, [r5, #DDRPHY_CA_DSKEW_CON0] str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x00006060 str r7, [r5, #DDRPHY_CA_DSKEW_CON2] - + b 12f +11: + ldr r7, =0x0 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] +12: ldr r7, =0x100007f str r7, [r5, #DDRPHY_OFFSETD_CON0] ldr r7, =0x7f @@ -222,12 +239,26 @@ ldr r7, =0x8 str r7, [r5, #DDRPHY_OFFSETW_CON2] + ldr r7, [r9, #ANADIG_DIGPROG] + and r7, r7, #0x11 + cmp r7, #0x10 + beq 13f + + ldr r7, =0x1c1c1c1c + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x30301c1c + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + ldr r7, =0x30303030 + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + b 14f +13: ldr r7, =0x08080808 str r7, [r5, #DDRPHY_CA_DSKEW_CON0] str r7, [r5, #DDRPHY_CA_DSKEW_CON1] ldr r7, =0x0808 str r7, [r5, #DDRPHY_CA_DSKEW_CON2] - +14: ldr r7, =0x11000008 str r7, [r5, #DDRPHY_OFFSETD_CON0] ldr r7, =0x10000008 @@ -243,7 +274,7 @@ .endm ENTRY(imx_lpddr3_freq_change) - push {r2 - r8} + push {r2 - r9} /* * To ensure no page table walks occur in DDR, we @@ -299,6 +330,7 @@ ENTRY(imx_lpddr3_freq_change) ldr r3, =IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR) ldr r4, =IMX_IO_P2V(MX7D_DDRC_BASE_ADDR) ldr r5, =IMX_IO_P2V(MX7D_DDRC_PHY_BASE_ADDR) + ldr r9, =IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR) ddrc_prepare @@ -380,6 +412,6 @@ done: nop /* Restore registers */ - pop {r2 - r8} + pop {r2 - r9} mov pc, lr ENDPROC(imx_lpddr3_freq_change) |