diff options
| author | Anson Huang <b20788@freescale.com> | 2016-10-27 13:55:15 +0300 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:21:26 +0800 |
| commit | a4d86eb119306d28e966add63c7b6e58e965934e (patch) | |
| tree | 6ee0cdd63dd9edc4b51f4d2eb1d9b6128f0d1bf1 /arch/arm/mach-imx/mx7.h | |
| parent | dc2bd69ba9f001e2c3891d6461f494d3ea9bbb0f (diff) | |
MLK-11265-6 ARM: imx: add imx7d msl support
Add MSL support for new SoC i.MX7D.
Signed-off-by: Anson Huang <b20788@freescale.com>
[Octavian: update upstream with minimal diff from mx_4.1.y to allow compile]
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/mx7.h')
| -rw-r--r-- | arch/arm/mach-imx/mx7.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx7.h b/arch/arm/mach-imx/mx7.h new file mode 100644 index 000000000000..97eff9cd7d8b --- /dev/null +++ b/arch/arm/mach-imx/mx7.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * * This program is free software; you can redistribute it and/or modify + * * it under the terms of the GNU General Public License version 2 as + * * published by the Free Software Foundation. + * */ + +#ifndef __ASM_ARCH_MX7_IOMAP_H__ +#define __ASM_ARCH_MX7_IOMAP_H__ + +#define MX7D_IO_P2V(x) IMX_IO_P2V(x) +#define MX7D_IO_ADDRESS(x) IOMEM(MX7D_IO_P2V(x)) + +#define MX7D_CCM_BASE_ADDR 0x30380000 +#define MX7D_CCM_SIZE 0x10000 +#define MX7D_IOMUXC_BASE_ADDR 0x30330000 +#define MX7D_IOMUXC_SIZE 0x10000 +#define MX7D_IOMUXC_GPR_BASE_ADDR 0x30340000 +#define MX7D_IOMUXC_GPR_SIZE 0x10000 +#define MX7D_ANATOP_BASE_ADDR 0x30360000 +#define MX7D_ANATOP_SIZE 0x10000 +#define MX7D_GPC_BASE_ADDR 0x303a0000 +#define MX7D_GPC_SIZE 0x10000 +#define MX7D_SRC_BASE_ADDR 0x30390000 +#define MX7D_SRC_SIZE 0x10000 +#define MX7D_DDRC_BASE_ADDR 0x307a0000 +#define MX7D_DDRC_SIZE 0x10000 +#define MX7D_DDRC_PHY_BASE_ADDR 0x30790000 +#define MX7D_DDRC_PHY_SIZE 0x10000 +#define MX7D_AIPS1_BASE_ADDR 0x30000000 +#define MX7D_AIPS1_SIZE 0x400000 +#define MX7D_AIPS2_BASE_ADDR 0x30400000 +#define MX7D_AIPS2_SIZE 0x400000 +#define MX7D_AIPS3_BASE_ADDR 0x30900000 +#define MX7D_AIPS3_SIZE 0x300000 + +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX7_IRAM_TLB_SIZE 0x4000 +#define MX7_SUSPEND_OCRAM_SIZE 0x1000 +#define MX7_CPUIDLE_OCRAM_ADDR_OFFSET 0x1000 +#define MX7_CPUIDLE_OCRAM_SIZE 0x1000 +#define MX7_BUSFREQ_OCRAM_ADDR_OFFSET 0x2000 +#define MX7_BUSFREQ_OCRAM_SIZE 0x1000 + +#endif |