diff options
| author | Anson Huang <b20788@freescale.com> | 2015-07-23 19:05:16 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:23:36 +0800 |
| commit | dba00e38b9ff89039bf4b1f0868b0821e1da349f (patch) | |
| tree | ff9d854b963b441610f188d2361a25cc0158314d /arch/arm/mach-imx/mx7.h | |
| parent | e3597059a3dab0454a2d980b5031c696637fe669 (diff) | |
MLK-11281-6 ARM: imx: add lpsr support for imx7d
Add LPSR mode support if dtb contains "fsl,enable-lpsr" property,
when echo mem to make system enter DSM mode, whole SOC will be
powered down except LPSR, SNVS domain and DDR chip's power,
that means all modules in SOC domain will be powered down,
including ccm, iomuxc, gpc....
So, all drivers need to restore their iomux settings and
clk settings after resume;
When system enters LPSR mode, can be waked up by long press
ON/OFF button or using RTC alarm.
In LPSR mode resume, ROM will read the entry point in LPSR
register, make DRAM exit retention mode and jump to DRAM
to resume kernel immediately, so before entering LPSR mode,
we need to set the resume entry correctly in LPSR register
and clear it after resume.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/mx7.h')
| -rw-r--r-- | arch/arm/mach-imx/mx7.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx7.h b/arch/arm/mach-imx/mx7.h index 97eff9cd7d8b..979a1c6bff7f 100644 --- a/arch/arm/mach-imx/mx7.h +++ b/arch/arm/mach-imx/mx7.h @@ -14,6 +14,8 @@ #define MX7D_IO_P2V(x) IMX_IO_P2V(x) #define MX7D_IO_ADDRESS(x) IOMEM(MX7D_IO_P2V(x)) +#define MX7D_LPSR_BASE_ADDR 0x30270000 +#define MX7D_LPSR_SIZE 0x10000 #define MX7D_CCM_BASE_ADDR 0x30380000 #define MX7D_CCM_SIZE 0x10000 #define MX7D_IOMUXC_BASE_ADDR 0x30330000 @@ -22,6 +24,8 @@ #define MX7D_IOMUXC_GPR_SIZE 0x10000 #define MX7D_ANATOP_BASE_ADDR 0x30360000 #define MX7D_ANATOP_SIZE 0x10000 +#define MX7D_SNVS_BASE_ADDR 0x30370000 +#define MX7D_SNVS_SIZE 0x10000 #define MX7D_GPC_BASE_ADDR 0x303a0000 #define MX7D_GPC_SIZE 0x10000 #define MX7D_SRC_BASE_ADDR 0x30390000 |