diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-05-08 14:26:33 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 11efbb4ec640d136aa4c27ef57cc7dbb7b8b3ecf (patch) | |
| tree | b70ff40472500156f8ba78b2a4b3ada4928f9907 /arch/arm/mach-imx/pm-imx7.c | |
| parent | f61538833e37831baaf704b06a6699cabdc4be18 (diff) | |
MLK-12748-3 ARM: imx: adjust imx7d lpddr3 retention exit flow
On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/pm-imx7.c')
| -rw-r--r-- | arch/arm/mach-imx/pm-imx7.c | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/pm-imx7.c b/arch/arm/mach-imx/pm-imx7.c index 8057cfb2fed7..ab3714225264 100644 --- a/arch/arm/mach-imx/pm-imx7.c +++ b/arch/arm/mach-imx/pm-imx7.c @@ -212,7 +212,7 @@ static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = { { 0x1a4, READ_DATA_FROM_HARDWARE }, { 0x1a8, READ_DATA_FROM_HARDWARE }, { 0x64, READ_DATA_FROM_HARDWARE }, - { 0xd0, 0xc0350001 }, + { 0xd0, READ_DATA_FROM_HARDWARE }, { 0xdc, READ_DATA_FROM_HARDWARE }, { 0xe0, READ_DATA_FROM_HARDWARE }, { 0xe4, READ_DATA_FROM_HARDWARE }, @@ -224,6 +224,7 @@ static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = { { 0x110, READ_DATA_FROM_HARDWARE }, { 0x114, READ_DATA_FROM_HARDWARE }, { 0x118, READ_DATA_FROM_HARDWARE }, + { 0x120, READ_DATA_FROM_HARDWARE }, { 0x11c, READ_DATA_FROM_HARDWARE }, { 0x180, READ_DATA_FROM_HARDWARE }, { 0x184, READ_DATA_FROM_HARDWARE }, @@ -231,9 +232,10 @@ static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = { { 0x194, READ_DATA_FROM_HARDWARE }, { 0x200, READ_DATA_FROM_HARDWARE }, { 0x204, READ_DATA_FROM_HARDWARE }, + { 0x210, READ_DATA_FROM_HARDWARE }, { 0x214, READ_DATA_FROM_HARDWARE }, { 0x218, READ_DATA_FROM_HARDWARE }, - { 0x240, 0x06000601 }, + { 0x240, READ_DATA_FROM_HARDWARE }, { 0x244, READ_DATA_FROM_HARDWARE }, }; @@ -242,6 +244,7 @@ static const u32 imx7d_ddrc_phy_lpddr3_setting[][2] __initconst = { { 0x4, READ_DATA_FROM_HARDWARE }, { 0x8, READ_DATA_FROM_HARDWARE }, { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, { 0x1c, READ_DATA_FROM_HARDWARE }, { 0x9c, READ_DATA_FROM_HARDWARE }, { 0x7c, READ_DATA_FROM_HARDWARE }, @@ -266,8 +269,8 @@ static const u32 imx7d_ddrc_ddr3_setting[][2] __initconst = { { 0x1a4, READ_DATA_FROM_HARDWARE }, { 0x1a8, READ_DATA_FROM_HARDWARE }, { 0x64, READ_DATA_FROM_HARDWARE }, - { 0x490, 0x00000001 }, - { 0xd0, 0xc0020001 }, + { 0x490, READ_DATA_FROM_HARDWARE }, + { 0xd0, READ_DATA_FROM_HARDWARE }, { 0xd4, READ_DATA_FROM_HARDWARE }, { 0xdc, READ_DATA_FROM_HARDWARE }, { 0xe0, READ_DATA_FROM_HARDWARE }, @@ -279,7 +282,7 @@ static const u32 imx7d_ddrc_ddr3_setting[][2] __initconst = { { 0x10c, READ_DATA_FROM_HARDWARE }, { 0x110, READ_DATA_FROM_HARDWARE }, { 0x114, READ_DATA_FROM_HARDWARE }, - { 0x120, 0x03030803 }, + { 0x120, READ_DATA_FROM_HARDWARE }, { 0x180, READ_DATA_FROM_HARDWARE }, { 0x190, READ_DATA_FROM_HARDWARE }, { 0x194, READ_DATA_FROM_HARDWARE }, @@ -287,7 +290,7 @@ static const u32 imx7d_ddrc_ddr3_setting[][2] __initconst = { { 0x204, READ_DATA_FROM_HARDWARE }, { 0x214, READ_DATA_FROM_HARDWARE }, { 0x218, READ_DATA_FROM_HARDWARE }, - { 0x240, 0x06000601 }, + { 0x240, READ_DATA_FROM_HARDWARE }, { 0x244, READ_DATA_FROM_HARDWARE }, }; @@ -295,6 +298,7 @@ static const u32 imx7d_ddrc_phy_ddr3_setting[][2] __initconst = { { 0x0, READ_DATA_FROM_HARDWARE }, { 0x4, READ_DATA_FROM_HARDWARE }, { 0x10, READ_DATA_FROM_HARDWARE }, + { 0xb0, READ_DATA_FROM_HARDWARE }, { 0x9c, READ_DATA_FROM_HARDWARE }, { 0x7c, READ_DATA_FROM_HARDWARE }, { 0x80, READ_DATA_FROM_HARDWARE }, @@ -1000,6 +1004,9 @@ static int __init imx7_suspend_init(const struct imx7_pm_socdata *socdata) ddrc_offset_array[i][0]); else pm_info->ddrc_val[i][1] = ddrc_offset_array[i][1]; + + if (pm_info->ddrc_val[i][0] == 0xd0) + pm_info->ddrc_val[i][1] |= 0xc0000000; } /* initialize DDRC PHY settings */ |