diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-02-19 12:56:04 +0100 |
|---|---|---|
| committer | Philippe Schenker <philippe.schenker@toradex.com> | 2019-05-24 11:34:16 +0200 |
| commit | d4ef9bf3b67efe4c6fe6e18fd176f2fb225efeac (patch) | |
| tree | 1bb0308b3399586d5bb93e3f87064f9ef8eaef33 /arch/arm/mach-imx | |
| parent | 5f6952acf04bee8054273801a5f9db66e57c13ff (diff) | |
ARM: imx: mach-imx7d: put external ethernet clock in error case
Exit early in case General-Purpose Registers are missing. This makes
sure that clock is always freed properly (clk_put).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/mach-imx7d.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index 58b62bc283bd..8293a9cafa2c 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -97,6 +97,12 @@ static void __init imx7d_enet_clk_sel(void) struct clk *enet_out_clk; struct regmap *gpr; + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (IS_ERR(gpr)) { + pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); + return; + } + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-fec"); if (!np) { pr_warn("%s: failed to find fec node\n", __func__); @@ -105,25 +111,19 @@ static void __init imx7d_enet_clk_sel(void) enet_out_clk = of_clk_get_by_name(np, "enet_out"); - gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); - - if (!IS_ERR(gpr)) { - if (IS_ERR(enet_out_clk)) { - pr_info("%s: failed to get enet_out clock, assuming ext. clock source\n", __func__); - /* use external clock for PHY */ - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK); - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); - } else { - pr_info("%s: found enet_out clock, assuming internal clock source\n", __func__); - /* use internal clock generation and output it to PHY */ - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, IMX7D_GPR1_ENET1_CLK_DIR_MASK); - clk_put(enet_out_clk); - - } + if (IS_ERR(enet_out_clk)) { + pr_info("%s: failed to get enet_out clock, assuming ext. clock source\n", __func__); + /* use external clock for PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK); + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); } else { - pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); + pr_info("%s: found enet_out clock, assuming internal clock source\n", __func__); + /* use internal clock generation and output it to PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, IMX7D_GPR1_ENET1_CLK_DIR_MASK); + clk_put(enet_out_clk); } + of_node_put(np); } |