diff options
| author | Juan Gutierrez <juan.gutierrez@nxp.com> | 2017-01-16 13:52:40 -0600 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:47 +0800 |
| commit | 9f748405b2b3be71fafbc630c9661794f9d93ff0 (patch) | |
| tree | 166a0fa907b2a1f6c73408cb42343300c5c3a397 /arch/arm/mach-imx | |
| parent | 39564133ecb45392f00a7c4849aa81f2f0261095 (diff) | |
MXSCM-243-2 arm: imx6q: mmdc handshake for lpddr2 2ch-mode on low-power
For i.mx6q systems the mmdc handshake on channel 0 is kept enabled (while
channel 1 is bypassed). This is ok for lpddr2 systems operating on 1ch-mode,
but not true for 2ch-mode. On this case the handshake needs to be set for
both channels, otherwise a kernel panic or Oops error might be observed
after resuming from suspend.
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/pm-imx6.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 83a8f82efb40..429910c02d78 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -685,6 +685,13 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else if (cpu_is_imx6q() && + imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 && + imx_mmdc_get_lpddr2_2ch_mode() == IMX_LPDDR2_2CH_MODE) { + /* keep handshake enabled for lpddr2 2ch-mode */ + val &= ~BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + val &= ~BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; @@ -703,6 +710,13 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else if (cpu_is_imx6q() && + imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 && + imx_mmdc_get_lpddr2_2ch_mode() == IMX_LPDDR2_2CH_MODE) { + /* keep handshake enabled for lpddr2 2ch-mode */ + val &= ~BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + val &= ~BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; |