MLK-10938-02 ARM: imx: add busfreq support for imx6ul

Add busfreq for i.MX6UL. As the CCM and MMDC of i.MX6UL reuse from i.MX6SX.
So most of the code can reuse from i.MX6SX. So rename the functions for i.MX6SX
to **_up, make it more common for using on i.MX6UL and i.MX6SX.

Signed-off-by: Bai Ping <b51503@freescale.com>

5 files changed, 129 insertions, 53 deletions

diff --git a/arch/arm/mach-imx/busfreq-imx.c b/arch/arm/mach-imx/busfreq-imx.c
index 1648e52ed936..5009267d8122 100644
--- a/arch/arm/mach-imx/busfreq-imx.c
+++ b/arch/arm/mach-imx/busfreq-imx.c
@@ -70,10 +70,10 @@ extern int unsigned long iram_tlb_base_addr;
 
 extern int init_mmdc_lpddr2_settings(struct platform_device *dev);
 extern int init_mmdc_ddr3_settings_imx6q(struct platform_device *dev);
-extern int init_mmdc_ddr3_settings_imx6sx(struct platform_device *dev);
+extern int init_mmdc_ddr3_settings_imx6_up(struct platform_device *dev);
 extern int init_ddrc_ddr_settings(struct platform_device *dev);
 extern int update_ddr_freq_imx_smp(int ddr_rate);
-extern int update_ddr_freq_imx6sx(int ddr_rate);
+extern int update_ddr_freq_imx6_up(int ddr_rate);
 extern int update_lpddr2_freq(int ddr_rate);
 
 DEFINE_MUTEX(bus_freq_mutex);
@@ -199,9 +199,13 @@ static void exit_lpm_imx7d(void)
 	clk_set_parent(dram_root, pll_dram);
 }
 
-static void enter_lpm_imx6sx(void)
+/*
+ * enter_lpm_imx6_up and exit_lpm_imx6_up is used by
+ * i.MX6SX/i.MX6UL for entering and exiting lpm mode.
+ */
+static void enter_lpm_imx6_up(void)
 {
-	if (imx_src_is_m4_enabled())
+	if (cpu_is_imx6sx() && imx_src_is_m4_enabled())
 		if (!check_m4_sleep())
 			pr_err("M4 is NOT in sleep!!!\n");
 
@@ -216,7 +220,7 @@ static void enter_lpm_imx6sx(void)
 		/* Need to ensure that PLL2_PFD_400M is kept ON. */
 		clk_prepare_enable(pll2_400);
 		if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
-			update_ddr_freq_imx6sx(LOW_AUDIO_CLK);
+			update_ddr_freq_imx6_up(LOW_AUDIO_CLK);
 		else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
 			update_lpddr2_freq(HIGH_AUDIO_CLK);
 		imx_clk_set_parent(periph2_clk2_sel, pll3);
@@ -242,7 +246,7 @@ static void enter_lpm_imx6sx(void)
 		cur_bus_freq_mode = BUS_FREQ_AUDIO;
 	} else {
 		if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
-			update_ddr_freq_imx6sx(LPAPM_CLK);
+			update_ddr_freq_imx6_up(LPAPM_CLK);
 		else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
 			update_lpddr2_freq(LPAPM_CLK);
 		imx_clk_set_parent(periph2_clk2_sel, osc_clk);
@@ -256,7 +260,7 @@ static void enter_lpm_imx6sx(void)
 	}
 }
 
-static void exit_lpm_imx6sx(void)
+static void exit_lpm_imx6_up(void)
 {
 	clk_prepare_enable(pll2_400);
 
@@ -273,7 +277,7 @@ static void exit_lpm_imx6sx(void)
 	imx_clk_set_parent(periph_clk, periph_pre_clk);
 
 	if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
-		update_ddr_freq_imx6sx(ddr_normal_rate);
+		update_ddr_freq_imx6_up(ddr_normal_rate);
 	else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
 		update_lpddr2_freq(ddr_normal_rate);
 	/* correct parent info after ddr freq change in asm code */
@@ -486,8 +490,8 @@ static void reduce_bus_freq(void)
 		enter_lpm_imx7d();
 	else if (cpu_is_imx6sl())
 		enter_lpm_imx6sl();
-	else if (cpu_is_imx6sx())
-		enter_lpm_imx6sx();
+	else if (cpu_is_imx6sx() || cpu_is_imx6ul())
+		enter_lpm_imx6_up();
 	else {
 		if (cpu_is_imx6dl())
 			/* Set axi to periph_clk */
@@ -612,8 +616,8 @@ static int set_high_bus_freq(int high_bus_freq)
 		exit_lpm_imx7d();
 	else if (cpu_is_imx6sl())
 		exit_lpm_imx6sl();
-	else if (cpu_is_imx6sx())
-		exit_lpm_imx6sx();
+	else if (cpu_is_imx6sx() || cpu_is_imx6ul())
+		exit_lpm_imx6_up();
 	else {
 		if (high_bus_freq) {
 			clk_prepare_enable(pll2_400);
@@ -1057,7 +1061,7 @@ static int busfreq_probe(struct platform_device *pdev)
 		}
 	}
 
-	if (cpu_is_imx6sl() || cpu_is_imx6sx()) {
+	if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul()) {
 		ahb_clk = devm_clk_get(&pdev->dev, "ahb");
 		if (IS_ERR(ahb_clk)) {
 			dev_err(busfreq_dev, "%s: failed to get ahb_clk\n",
@@ -1168,7 +1172,7 @@ static int busfreq_probe(struct platform_device *pdev)
 			return PTR_ERR(pll2_bypass);
 		}
 	}
-	if (cpu_is_imx6sx()) {
+	if (cpu_is_imx6sx() || cpu_is_imx6ul()) {
 		mmdc_clk = devm_clk_get(&pdev->dev, "mmdc");
 		if (IS_ERR(mmdc_clk)) {
 			dev_err(busfreq_dev,
@@ -1176,6 +1180,8 @@ static int busfreq_probe(struct platform_device *pdev)
 				__func__);
 			return PTR_ERR(mmdc_clk);
 		}
+	}
+	if (cpu_is_imx6sx()) {
 		m4_clk = devm_clk_get(&pdev->dev, "m4");
 		if (IS_ERR(m4_clk)) {
 			dev_err(busfreq_dev,
@@ -1268,19 +1274,22 @@ static int busfreq_probe(struct platform_device *pdev)
 		err = init_ddrc_ddr_settings(pdev);
 	} else if (cpu_is_imx6sl()) {
 		err = init_mmdc_lpddr2_settings(pdev);
-	} else if (cpu_is_imx6sx()) {
+	} else if (cpu_is_imx6sx() || cpu_is_imx6ul()) {
 		ddr_type = imx_mmdc_get_ddr_type();
 		/* check whether it is a DDR3 or LPDDR2 board */
 		if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
-			err = init_mmdc_ddr3_settings_imx6sx(pdev);
+			err = init_mmdc_ddr3_settings_imx6_up(pdev);
 		else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
 			err = init_mmdc_lpddr2_settings(pdev);
+	} else {
+		err = init_mmdc_ddr3_settings_imx6q(pdev);
+	}
+
+	if (cpu_is_imx6sx()) {
 		/* if M4 is enabled and rate > 24MHz, add high bus count */
 		if (imx_src_is_m4_enabled() &&
 			(clk_get_rate(m4_clk) > LPAPM_CLK))
 			high_bus_count++;
-	} else {
-		err = init_mmdc_ddr3_settings_imx6q(pdev);
 	}
 
 	if (err) {
diff --git a/arch/arm/mach-imx/busfreq_ddr3.c b/arch/arm/mach-imx/busfreq_ddr3.c
index b26163d06a1d..81c08e4293ea 100644
--- a/arch/arm/mach-imx/busfreq_ddr3.c
+++ b/arch/arm/mach-imx/busfreq_ddr3.c
@@ -62,7 +62,7 @@ struct imx6_busfreq_info {
 	u32 mu_delay_val;
 } __aligned(8);
 
-static struct imx6_busfreq_info *imx6sx_busfreq_info;
+static struct imx6_busfreq_info *imx6_busfreq_info;
 
 /* DDR settings */
 static unsigned long (*iram_ddr_settings)[2];
@@ -77,8 +77,8 @@ static int ddr_settings_size;
 static int iomux_settings_size;
 static int curr_ddr_rate;
 
-void (*imx6sx_change_ddr_freq)(struct imx6_busfreq_info *busfreq_info);
-extern void imx6sx_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info);
+void (*imx6_up_change_ddr_freq)(struct imx6_busfreq_info *busfreq_info);
+extern void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info);
 
 void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings,
 	bool dll_mode, void *iomux_offsets) = NULL;
@@ -104,8 +104,8 @@ extern unsigned long iram_tlb_phys_addr;
 
 extern unsigned long mx6_ddr3_freq_change_start asm("mx6_ddr3_freq_change_start");
 extern unsigned long mx6_ddr3_freq_change_end asm("mx6_ddr3_freq_change_end");
-extern unsigned long imx6sx_ddr3_freq_change_start asm("imx6sx_ddr3_freq_change_start");
-extern unsigned long imx6sx_ddr3_freq_change_end asm("imx6sx_ddr3_freq_change_end");
+extern unsigned long imx6_up_ddr3_freq_change_start asm("imx6_up_ddr3_freq_change_start");
+extern unsigned long imx6_up_ddr3_freq_change_end asm("imx6_up_ddr3_freq_change_end");
 #ifdef CONFIG_SMP
 static unsigned long wfe_freq_change_iram_base;
 volatile u32 *wait_for_ddr_freq_update;
@@ -151,6 +151,11 @@ unsigned long iomux_offsets_mx6sx[][2] = {
 	{0x33c, 0x0},
 };
 
+unsigned long iomux_offsets_mx6ul[][2] = {
+	{0x280, 0x0},
+	{0x284, 0x0},
+};
+
 unsigned long ddr3_dll_mx6q[][2] = {
 	{0x0c, 0x0},
 	{0x10, 0x0},
@@ -252,7 +257,8 @@ static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id)
 }
 #endif
 
-int update_ddr_freq_imx6sx(int ddr_rate)
+/* Used by i.MX6SX/i.MX6UL for updating the ddr frequency */
+int update_ddr_freq_imx6_up(int ddr_rate)
 {
 	int i;
 	bool dll_off = false;
@@ -267,7 +273,7 @@ int update_ddr_freq_imx6sx(int ddr_rate)
 	if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO))
 		dll_off = true;
 
-	imx6sx_busfreq_info->dll_off = dll_off;
+	imx6_busfreq_info->dll_off = dll_off;
 	iram_ddr_settings[0][0] = ddr_settings_size;
 	iram_iomux_settings[0][0] = iomux_settings_size;
 	for (i = 0; i < iram_ddr_settings[0][0]; i++) {
@@ -280,13 +286,13 @@ int update_ddr_freq_imx6sx(int ddr_rate)
 	local_irq_disable();
 
 	ttbr1 = save_ttbr1();
-	imx6sx_busfreq_info->freq = ddr_rate;
-	imx6sx_busfreq_info->ddr_settings = iram_ddr_settings;
-	imx6sx_busfreq_info->iomux_offsets = iram_iomux_settings;
-	imx6sx_busfreq_info->mu_delay_val  = ((readl_relaxed(mmdc_base + MMDC0_MPMUR0)
+	imx6_busfreq_info->freq = ddr_rate;
+	imx6_busfreq_info->ddr_settings = iram_ddr_settings;
+	imx6_busfreq_info->iomux_offsets = iram_iomux_settings;
+	imx6_busfreq_info->mu_delay_val  = ((readl_relaxed(mmdc_base + MMDC0_MPMUR0)
 		>> MMDC0_MPMUR0_OFFSET) & MMDC0_MPMUR0_MASK);
 
-	imx6sx_change_ddr_freq(imx6sx_busfreq_info);
+	imx6_up_change_ddr_freq(imx6_busfreq_info);
 	restore_ttbr1(ttbr1);
 	curr_ddr_rate = ddr_rate;
 
@@ -433,7 +439,8 @@ int update_ddr_freq_imx_smp(int ddr_rate)
 	return 0;
 }
 
-int init_mmdc_ddr3_settings_imx6sx(struct platform_device *busfreq_pdev)
+/* Used by i.MX6SX/i.MX6UL for mmdc setting init. */
+int init_mmdc_ddr3_settings_imx6_up(struct platform_device *busfreq_pdev)
 {
 	int i;
 	struct device_node *node;
@@ -447,7 +454,10 @@ int init_mmdc_ddr3_settings_imx6sx(struct platform_device *busfreq_pdev)
 	mmdc_base = of_iomap(node, 0);
 	WARN(!mmdc_base, "unable to map mmdc registers\n");
 
-	node = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-iomuxc");
+	if (cpu_is_imx6sx())
+		node = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-iomuxc");
+	else
+		node = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-iomuxc");
 	if (!node) {
 		printk(KERN_ERR "failed to find iomuxc device tree data!\n");
 		return -EINVAL;
@@ -477,15 +487,18 @@ int init_mmdc_ddr3_settings_imx6sx(struct platform_device *busfreq_pdev)
 				+ normal_mmdc_settings[i][0]);
 	}
 
-	iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6sx);
+	if (cpu_is_imx6ul())
+		iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6ul);
+	else
+		iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6sx);
 
-	ddr_code_size = (&imx6sx_ddr3_freq_change_end -&imx6sx_ddr3_freq_change_start) *4 +
-			sizeof(*imx6sx_busfreq_info);
+	ddr_code_size = (&imx6_up_ddr3_freq_change_end -&imx6_up_ddr3_freq_change_start) *4 +
+			sizeof(*imx6_busfreq_info);
 
-	imx6sx_busfreq_info = (struct imx6_busfreq_info *)ddr_freq_change_iram_base;
+	imx6_busfreq_info = (struct imx6_busfreq_info *)ddr_freq_change_iram_base;
 
-	imx6sx_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + sizeof(*imx6sx_busfreq_info),
-		&imx6sx_ddr3_freq_change, ddr_code_size - sizeof(*imx6sx_busfreq_info));
+	imx6_up_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + sizeof(*imx6_busfreq_info),
+		&imx6_up_ddr3_freq_change, ddr_code_size - sizeof(*imx6_busfreq_info));
 
 	/*
 	 * Store the size of the array in iRAM also,
@@ -501,13 +514,23 @@ int init_mmdc_ddr3_settings_imx6sx(struct platform_device *busfreq_pdev)
 	}
 
 	for (i = 0; i < iomux_settings_size; i++) {
-		iomux_offsets_mx6sx[i][1] =
+		if (cpu_is_imx6ul()) {
+			iomux_offsets_mx6ul[i][1] =
 			readl_relaxed(iomux_base +
+				iomux_offsets_mx6ul[i][0]);
+			iram_iomux_settings[i + 1][0] =
+				iomux_offsets_mx6ul[i][0];
+			iram_iomux_settings[i + 1][1] =
+				iomux_offsets_mx6ul[i][1];
+		} else {
+			iomux_offsets_mx6sx[i][1] =
+				readl_relaxed(iomux_base +
 				iomux_offsets_mx6sx[i][0]);
-		iram_iomux_settings[i + 1][0] =
+			iram_iomux_settings[i + 1][0] =
 				iomux_offsets_mx6sx[i][0];
 			iram_iomux_settings[i + 1][1] =
 				iomux_offsets_mx6sx[i][1];
+		}
 	}
 
 	curr_ddr_rate = ddr_normal_rate;
diff --git a/arch/arm/mach-imx/busfreq_lpddr2.c b/arch/arm/mach-imx/busfreq_lpddr2.c
index c4343bcd9cfb..299804c55d8d 100644
--- a/arch/arm/mach-imx/busfreq_lpddr2.c
+++ b/arch/arm/mach-imx/busfreq_lpddr2.c
@@ -52,7 +52,7 @@ void (*mx6_change_lpddr2_freq)(u32 ddr_freq, int bus_freq_mode) = NULL;
 
 extern unsigned int ddr_normal_rate;
 extern void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode);
-extern void imx6sx_lpddr2_freq_change(u32 freq, int bus_freq_mode);
+extern void imx6_up_lpddr2_freq_change(u32 freq, int bus_freq_mode);
 extern unsigned long save_ttbr1(void);
 extern void restore_ttbr1(unsigned long ttbr1);
 extern unsigned long ddr_freq_change_iram_base;
@@ -101,10 +101,10 @@ int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev)
 		mx6_change_lpddr2_freq = (void *)fncpy(
 			(void *)ddr_freq_change_iram_base,
 			&mx6_lpddr2_freq_change, ddr_code_size);
-	else if (cpu_is_imx6sx())
+	else if (cpu_is_imx6sx() || cpu_is_imx6ul())
 		mx6_change_lpddr2_freq = (void *)fncpy(
 			(void *)ddr_freq_change_iram_base,
-			&imx6sx_lpddr2_freq_change, ddr_code_size);
+			&imx6_up_lpddr2_freq_change, ddr_code_size);
 
 	curr_ddr_rate = ddr_normal_rate;
 
diff --git a/arch/arm/mach-imx/ddr3_freq_imx6sx.S b/arch/arm/mach-imx/ddr3_freq_imx6sx.S
index 2db7fe10ceab..4dc89b9c3744 100644
--- a/arch/arm/mach-imx/ddr3_freq_imx6sx.S
+++ b/arch/arm/mach-imx/ddr3_freq_imx6sx.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,8 +15,8 @@
 #include <linux/linkage.h>
 #include "hardware.h"
 
-.globl imx6sx_ddr3_freq_change_start
-.globl imx6sx_ddr3_freq_change_end
+.globl imx6_up_ddr3_freq_change_start
+.globl imx6_up_ddr3_freq_change_end
 
 #define MMDC0_MDPDC		0x4
 #define MMDC0_MDCF0		0xc
@@ -47,6 +47,18 @@
 
 	.align 3
 
+	/* Check if the cpu is cortex-a7 */
+	.macro is_ca7
+
+	/* Read the primary cpu number is MPIDR */
+	mrc	p15, 0, r7, c0, c0, 0
+	ldr	r8, =0xfff0
+	and	r7, r7, r8
+	ldr	r8, =0xc070
+	cmp	r7, r8
+
+	.endm
+
 	.macro do_delay
 
 1:
@@ -160,15 +172,16 @@ skip_periph2_clk2_switch_50m:
 	.endm
 
 /*
- *  imx6sx_ddr3_freq_change
+ *  imx6_up_ddr3_freq_change
+ *  Below code can be used by i.MX6SX and i.MX6UL.
  *
  *  idle the processor (eg, wait for interrupt).
  *  make sure DDR is in self-refresh.
  *  IRQs are already disabled.
  */
-ENTRY(imx6sx_ddr3_freq_change)
+ENTRY(imx6_up_ddr3_freq_change)
 
-imx6sx_ddr3_freq_change_start:
+imx6_up_ddr3_freq_change_start:
 	stmfd	sp!, {r4 - r11}
 
 	ldr	r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET]
@@ -230,6 +243,9 @@ imx6sx_ddr3_freq_change_start:
 	ldr	r5, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
 	ldr	r6, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR)
 
+	is_ca7
+	beq	skip_disable_l2
+
 #ifdef CONFIG_CACHE_L2X0
 	/*
 	 * make sure the L2 buffers are drained,
@@ -258,6 +274,7 @@ wait_for_l2_to_idle:
 	isb
 #endif
 
+skip_disable_l2:
 	/* disable automatic power saving. */
 	ldr	r8, [r4, #MMDC0_MAPSR]
 	orr	r8, r8, #0x1
@@ -660,6 +677,9 @@ done:
 	bic	r8, r8, #0x01
 	str	r8, [r4, #MMDC0_MAPSR]
 
+	is_ca7
+	beq	skip_enable_l2
+
 #ifdef CONFIG_CACHE_L2X0
 	/* Enable L2. */
 	ldr	r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
@@ -667,6 +687,7 @@ done:
 	str	r7, [r8, #0x100]
 #endif
 
+skip_enable_l2:
 	/* Enable L1 data cache. */
 	mrc	p15, 0, r7, c1, c0, 0
 	orr	r7, r7, #0x4
@@ -710,5 +731,5 @@ done:
 	 * within the text space.
 	 */
 	.ltorg
-imx6sx_ddr3_freq_change_end:
-ENDPROC(imx6sx_ddr3_freq_change)
+imx6_up_ddr3_freq_change_end:
+ENDPROC(imx6_up_ddr3_freq_change)
diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6sx.S b/arch/arm/mach-imx/lpddr2_freq_imx6sx.S
index cf3e8fcd3d8c..2c78aac23ad0 100644
--- a/arch/arm/mach-imx/lpddr2_freq_imx6sx.S
+++ b/arch/arm/mach-imx/lpddr2_freq_imx6sx.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,6 +26,18 @@
 #define MMDC0_MAPSR	0x404
 #define MMDC0_MADPCR0	0x410
 
+	/* Check if the cpu is cortex-a7 */
+	.macro is_ca7
+
+	/* Read the primary cpu number is MPIDR */
+	mrc	p15, 0, r6, c0, c0, 0
+	ldr	r7, =0xfff0
+	and	r6, r6, r7
+	ldr	r7, =0xc070
+	cmp	r6, r7
+
+	.endm
+
 	.macro	wait_for_ccm_handshake
 
 1:
@@ -201,7 +213,11 @@ force_measure1:
 	.endm
 
 	.align 3
-ENTRY(imx6sx_lpddr2_freq_change)
+/*
+ * Below code can be used by i.MX6SX and i.MX6UL when changing the
+ * frequency of MMDC. the MMDC is the same on these two SOCs.
+ */
+ENTRY(imx6_up_lpddr2_freq_change)
 
 	push	{r2 - r8}
 
@@ -255,6 +271,9 @@ ENTRY(imx6sx_lpddr2_freq_change)
 	dsb
 	isb
 
+	is_ca7
+	beq	skip_disable_l2
+
 #ifdef CONFIG_CACHE_L2X0
 	/*
 	 * Need to make sure the buffers in L2 are drained.
@@ -275,6 +294,7 @@ ENTRY(imx6sx_lpddr2_freq_change)
 	str	r6, [r7, #0x100]
 #endif
 
+skip_disable_l2:
 	ldr	r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
 	ldr	r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR)
 	ldr	r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
@@ -375,6 +395,8 @@ skip_power_down:
 	bic	r6, r6, #0x100
 	str	r6, [r5, #MMDC0_MADPCR0]
 
+	is_ca7
+	beq	skip_enable_l2
 
 #ifdef CONFIG_CACHE_L2X0
 	/* Enable L2. */
@@ -383,6 +405,7 @@ skip_power_down:
 	str	r6, [r7, #0x100]
 #endif
 
+skip_enable_l2:
 	/* Enable L1 data cache. */
 	mrc	p15, 0, r6, c1, c0, 0
 	orr	r6, r6, #0x4