diff options
| author | Stepan Moskovchenko <stepanm@codeaurora.org> | 2010-11-15 18:19:35 -0800 |
|---|---|---|
| committer | Daniel Walker <dwalker@codeaurora.org> | 2010-11-30 16:05:05 -0800 |
| commit | 08bd6839783319085ee0db4c888534e626225774 (patch) | |
| tree | 74f0374f4905a45bad209868fac45adb9ed333a2 /arch/arm/mach-msm/include/mach/iommu.h | |
| parent | 0ab84745ef65043a616b36b26bec58e1cb62a742 (diff) | |
msm: iommu: Definitions for extended memory attributes
Add the register field definitions and memory attribute
definitions that will be needed to support IOMMU
transactions with cache-coherent memory access.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm/include/mach/iommu.h')
| -rw-r--r-- | arch/arm/mach-msm/include/mach/iommu.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 17fc79fc8bc2..296c0f10f230 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -20,6 +20,19 @@ #include <linux/interrupt.h> +/* Sharability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NON_SH 0x0 +#define MSM_IOMMU_ATTR_SH 0x4 + +/* Cacheability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NONCACHED 0x0 +#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 +#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 +#define MSM_IOMMU_ATTR_CACHED_WT 0x3 + +/* Mask for the cache policy attribute */ +#define MSM_IOMMU_CP_MASK 0x03 + /* Maximum number of Machine IDs that we are allowing to be mapped to the same * context bank. The number of MIDs mapped to the same CB does not affect * performance, but there is a practical limit on how many distinct MIDs may |