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authorLennert Buytenhek <buytenh@wantstofly.org>2009-02-20 02:31:58 +0100
committerNicolas Pitre <nico@cam.org>2009-02-19 22:41:37 -0500
commit712424fd95134bf88d27f3885389fe6ab13f34ac (patch)
tree8b146e05b2f2810bddd1c55f30764a690a534a7f /arch/arm/mach-mv78xx0/db78x00-bp-setup.c
parentcfdeb6376e439c58c2d37de492d2a8c763621022 (diff)
[ARM] mv78xx0: force eth2/eth3 to PHYless mode on pre-A0 silicon
On pre-A0 revisions of the mv78xx0 SoC, the third and fourth ethernet interface are not brought out to pins, but are internally cross-connected, so if we run on pre-A0 silicon, we'll force eth2 and eth3 to PHYless mode. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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