diff options
author | Alison Wang <b18965@freescale.com> | 2012-07-26 15:24:38 +0800 |
---|---|---|
committer | Justin Waters <justin.waters@timesys.com> | 2012-09-12 16:49:39 -0400 |
commit | e426e71b4fe2b2907cba29f7be472e68efe2e47e (patch) | |
tree | c29b3a4647969a83e808803dbcb2d665cd0b0f30 /arch/arm/mach-mvf | |
parent | f01398b9af3cc8ad75bb60628753dc517a952c5a (diff) |
ENGR00180931-1 mvf: add MSL support for MVF platform
Add MSL support for MVF platform.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Diffstat (limited to 'arch/arm/mach-mvf')
-rw-r--r-- | arch/arm/mach-mvf/Kconfig | 61 | ||||
-rw-r--r-- | arch/arm/mach-mvf/Makefile | 9 | ||||
-rw-r--r-- | arch/arm/mach-mvf/Makefile.boot | 3 | ||||
-rw-r--r-- | arch/arm/mach-mvf/board-twr-vf700.c | 395 | ||||
-rw-r--r-- | arch/arm/mach-mvf/bus_freq.c | 65 | ||||
-rw-r--r-- | arch/arm/mach-mvf/clock.c | 1740 | ||||
-rw-r--r-- | arch/arm/mach-mvf/cpu.c | 92 | ||||
-rw-r--r-- | arch/arm/mach-mvf/crm_regs.h | 536 | ||||
-rw-r--r-- | arch/arm/mach-mvf/devices-mvf.h | 209 | ||||
-rw-r--r-- | arch/arm/mach-mvf/devices.c | 78 | ||||
-rw-r--r-- | arch/arm/mach-mvf/dummy_gpio.c | 124 | ||||
-rw-r--r-- | arch/arm/mach-mvf/irq.c | 67 | ||||
-rw-r--r-- | arch/arm/mach-mvf/mm.c | 89 | ||||
-rw-r--r-- | arch/arm/mach-mvf/regs-anadig.h | 1008 | ||||
-rw-r--r-- | arch/arm/mach-mvf/system.c | 36 |
15 files changed, 4512 insertions, 0 deletions
diff --git a/arch/arm/mach-mvf/Kconfig b/arch/arm/mach-mvf/Kconfig new file mode 100644 index 000000000000..10ec5b6307df --- /dev/null +++ b/arch/arm/mach-mvf/Kconfig @@ -0,0 +1,61 @@ +if ARCH_MVF + +config ARCH_MVFA5 + bool + select USB_ARCH_HAS_EHCI + select ARCH_MXC_IOMUX_V3 + select ARCH_MXC_AUDMUX_V2 + select ARM_GIC + select ARCH_HAS_CPUFREQ + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_FEC + select IMX_HAVE_PLATFORM_IMX_IPUV3 + select IMX_HAVE_PLATFORM_MXC_PWM + select IMX_HAVE_PLATFORM_LDB + select IMX_HAVE_PLATFORM_IMX_SPDIF + select IMX_HAVE_PLATFORM_MVF_SPI + select IMX_HAVE_PLATFORM_MVF_DCU + select IMX_HAVE_PLATFORM_MVF_SAI + select HAVE_PIT + +config FORCE_MAX_ZONEORDER + int "MAX_ORDER" + default "13" + +config SOC_MVFA5 + bool + +config MACH_MVFA5_TWR_VF700 + bool "Support MVF CORTEX-A5 TWR-VF700 platform" + select ARCH_MVFA5 + select SOC_MVFA5 + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_DMA + select IMX_HAVE_PLATFORM_FEC + select IMX_HAVE_PLATFORM_GPMI_NFC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_VIV_GPU + select IMX_HAVE_PLATFORM_IMX_VPU + select IMX_HAVE_PLATFORM_IMX_SSI + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_FSL_OTG + select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP + select IMX_HAVE_PLATFORM_AHCI + select IMX_HAVE_PLATFORM_IMX_OCOTP + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_SNVS_RTC + select IMX_HAVE_PLATFORM_IMX_PM + select IMX_HAVE_PLATFORM_MXC_HDMI + select IMX_HAVE_PLATFORM_IMX_ASRC + select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_MVF_SPI + select IMX_HAVE_PLATFORM_MVF_DCU + select IMX_HAVE_PLATFORM_MVF_SAI + select IMX_HAVE_PLATFORM_MXC_NAND + help + Include support for MVF TWR-VF700 platform. This includes specific + configurations for the board and its peripherals. + +endif diff --git a/arch/arm/mach-mvf/Makefile b/arch/arm/mach-mvf/Makefile new file mode 100644 index 000000000000..b6c048ba364b --- /dev/null +++ b/arch/arm/mach-mvf/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. +obj-y := cpu.o mm.o system.o devices.o dummy_gpio.o irq.o bus_freq.o mvf_fec.o usb_dr.o usb_dr2.o + +obj-$(CONFIG_ARCH_MVFA5) += clock.o +obj-$(CONFIG_MACH_MVFA5_TWR_VF700) += board-twr-vf700.o diff --git a/arch/arm/mach-mvf/Makefile.boot b/arch/arm/mach-mvf/Makefile.boot new file mode 100644 index 000000000000..4bcb1cdecf45 --- /dev/null +++ b/arch/arm/mach-mvf/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-$(CONFIG_ARCH_MVFA5) := 0x80008000 +params_phys-$(CONFIG_ARCH_MVFA5) := 0x80000100 +initrd_phys-$(CONFIG_ARCH_MVFA5) := 0x80800000 diff --git a/arch/arm/mach-mvf/board-twr-vf700.c b/arch/arm/mach-mvf/board-twr-vf700.c new file mode 100644 index 000000000000..f1848177196e --- /dev/null +++ b/arch/arm/mach-mvf/board-twr-vf700.c @@ -0,0 +1,395 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/nodemask.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/smsc911x.h> +#include <linux/spi/spi.h> +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +#include <linux/spi/flash.h> +#else +#include <linux/mtd/physmap.h> +#endif +#include <linux/i2c.h> +#include <linux/i2c/pca953x.h> +#include <linux/ata.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/map.h> +#include <linux/mtd/partitions.h> +#include <linux/pmic_external.h> +#include <linux/pmic_status.h> +#include <linux/ipu.h> +#include <linux/mxcfb.h> +#include <linux/pwm_backlight.h> +#include <linux/fec.h> +#include <linux/memblock.h> +#include <linux/gpio.h> +#include <linux/etherdevice.h> +#include <linux/regulator/anatop-regulator.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <sound/pcm.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/mxc_dvfs.h> +#include <mach/memory.h> +#include <mach/iomux-mvf.h> +#include <mach/imx-uart.h> +#include <mach/spi-mvf.h> +#include <mach/viv_gpu.h> +#include <mach/ahci_sata.h> +#include <mach/ipu-v3.h> +#include <mach/mxc_hdmi.h> +#include <mach/mxc_asrc.h> +#include <mach/mipi_dsi.h> +#include <mach/mipi_csi2.h> + +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "devices-mvf.h" +#include "usb.h" +#include "crm_regs.h" + +#define MVF600_SD1_CD 134 + + +static iomux_v3_cfg_t mvf600_pads[] = { + + /*SDHC1*/ + MVF600_PAD14_PTA24__SDHC1_CLK, + MVF600_PAD15_PTA25__SDHC1_CMD, + MVF600_PAD16_PTA26__SDHC1_DAT0, + MVF600_PAD17_PTA27__SDHC1_DAT1, + MVF600_PAD18_PTA28__SDHC1_DAT2, + MVF600_PAD19_PTA29__SDHC1_DAT3, + /*set PTA7 as GPIO for sdhc card detecting*/ + MVF600_PAD134_PTA7__SDHC1_SW_CD, + + /*I2C0*/ + MVF600_PAD36_PTB14__I2C0_SCL, + MVF600_PAD37_PTB15__I2C0_SDA, + +#if 0 + /*CAN1*/ + MVF600_PAD38_PTB16__CAN1_RX, + MVF600_PAD39_PTB17__CAN1_TX, + + /*DSPI0*/ + MVF600_PAD41_PTB19__DSPI0_PCS0, + MVF600_PAD42_PTB20__DSPI0_SIN, + MVF600_PAD43_PTB21__DSPI0_SOUT, + MVF600_PAD44_PTB22__DSPI0_SCK, +#endif + /*FEC0*/ + MVF600_PAD0_PTA6__RMII_CLKIN, + MVF600_PAD45_PTC0__RMII0_MDC, + MVF600_PAD46_PTC1__RMII0_MDIO, + MVF600_PAD47_PTC2__RMII0_CRS_DV, + MVF600_PAD48_PTC3__RMII0_RXD1, + MVF600_PAD49_PTC4__RMII0_RXD0, + MVF600_PAD50_PTC5__RMII0_RXER, + MVF600_PAD51_PTC6__RMII0_TXD1, + MVF600_PAD52_PTC7__RMII0_TXD0, + MVF600_PAD53_PTC8__RMII0_TXEN, + + /*SAI2*/ + MVF600_PAD6_PTA16_SAI2_TX_BCLK, + MVF600_PAD8_PTA18_SAI2_TX_DATA, + MVF600_PAD9_PTA19_SAI2_TX_SYNC, + MVF600_PAD11_PTA21_SAI2_RX_BCLK, + MVF600_PAD12_PTA22_SAI2_RX_DATA, + MVF600_PAD13_PTA23_SAI2_RX_SYNC, + MVF600_PAD40_PTB18_EXT_AUDIO_MCLK, + + /*DCU0*/ + MVF600_PAD30_PTB8_LCD_ENABLE, + MVF600_PAD105_PTE0_DCU0_HSYNC, + MVF600_PAD106_PTE1_DCU0_VSYNC, + MVF600_PAD107_PTE2_DCU0_PCLK, + MVF600_PAD109_PTE4_DCU0_DE, + MVF600_PAD110_PTE5_DCU0_R0, + MVF600_PAD111_PTE6_DCU0_R1, + MVF600_PAD112_PTE7_DCU0_R2, + MVF600_PAD113_PTE8_DCU0_R3, + MVF600_PAD114_PTE9_DCU0_R4, + MVF600_PAD115_PTE10_DCU0_R5, + MVF600_PAD116_PTE11_DCU0_R6, + MVF600_PAD117_PTE12_DCU0_R7, + MVF600_PAD118_PTE13_DCU0_G0, + MVF600_PAD119_PTE14_DCU0_G1, + MVF600_PAD120_PTE15_DCU0_G2, + MVF600_PAD121_PTE16_DCU0_G3, + MVF600_PAD122_PTE17_DCU0_G4, + MVF600_PAD123_PTE18_DCU0_G5, + MVF600_PAD124_PTE19_DCU0_G6, + MVF600_PAD125_PTE20_DCU0_G7, + MVF600_PAD126_PTE21_DCU0_B0, + MVF600_PAD127_PTE22_DCU0_B1, + MVF600_PAD128_PTE23_DCU0_B2, + MVF600_PAD129_PTE24_DCU0_B3, + MVF600_PAD130_PTE25_DCU0_B4, + MVF600_PAD131_PTE26_DCU0_B5, + MVF600_PAD132_PTE27_DCU0_B6, + MVF600_PAD133_PTE28_DCU0_B7, + + /*UART1*/ + MVF600_PAD26_PTB4_UART1_TX, + MVF600_PAD27_PTB5_UART1_RX, + + /*USB0/1 VBUS_EN*/ + MVF600_PAD85_PTD6__USB0_VBUS_EN, + MVF600_PAD92_PTD13__USB1_VBUS_EN, +}; + +static struct mxc_audio_platform_data mvf_twr_audio_data; + +static int mvf_twr_sgtl5000_init(void) +{ + mvf_twr_audio_data.sysclk = 24576000; + return 0; +} + +static struct mvf_sai_platform_data mvf_sai_pdata = { + .flags = MVF_SAI_DMA | MVF_SAI_TRA_SYN | MVF_SAI_USE_I2S_SLAVE, +}; + +static struct mxc_audio_platform_data mvf_twr_audio_data = { + .sai_num = 1, + .src_port = 2, + .ext_port = 2, + .init = mvf_twr_sgtl5000_init, +}; + +static struct platform_device mvf_twr_audio_device = { + .name = "mvf-sgtl5000", +}; + +static inline void mvf_vf700_init_uart(void) +{ + mvf_add_imx_uart(1, NULL); +} + +static int mvf_vf700_fec_phy_init(struct phy_device *phydev) +{ +/* prefer master mode, 1000 Base-T capable */ + phy_write(phydev, 0x9, 0x0f00); + + /* min rx data delay */ + phy_write(phydev, 0x0b, 0x8105); + phy_write(phydev, 0x0c, 0x0000); + + /* max rx/tx clock delay, min rx/tx control delay */ + phy_write(phydev, 0x0b, 0x8104); + phy_write(phydev, 0x0c, 0xf0f0); + phy_write(phydev, 0x0b, 0x104); + + return 0; +} + +static int mvf_vf700_fec_power_hibernate(struct phy_device *phydev) +{ + return 0; +} + +static struct fec_platform_data fec_data __initdata = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static int mvf_vf700_spi_cs[] = { +}; + +static const struct spi_mvf_master mvf_vf700_spi_data __initconst = { + .bus_num = 0, + .chipselect = mvf_vf700_spi_cs, + .num_chipselect = ARRAY_SIZE(mvf_vf700_spi_cs), + .cs_control = NULL, +}; + +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +static struct mtd_partition m25p32_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x00040000, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data m25p32_spi_flash_data = { + .name = "m25p32", + .parts = m25p32_partitions, + .nr_parts = ARRAY_SIZE(m25p32_partitions), + .type = "m25p32", +}; +#endif + +static struct spi_board_info mvf_spi_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) + { + /* The modalias must be the same as spi device driver name */ + .modalias = "m25p80", + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + .platform_data = &m25p32_spi_flash_data, + }, +#endif +}; +static void spi_device_init(void) +{ + spi_register_board_info(mvf_spi_board_info, + ARRAY_SIZE(mvf_spi_board_info)); +} + +#if 1 +static void vf700_suspend_enter(void) +{ + /* suspend preparation */ +} + +static void vf700_suspend_exit(void) +{ + /* resmue resore */ +} +static const struct pm_platform_data mvf_vf700_pm_data __initconst = { + .name = "mvf_pm", + .suspend_enter = vf700_suspend_enter, + .suspend_exit = vf700_suspend_exit, +}; +#endif + +static struct mvf_dcu_platform_data mvf_dcu_pdata = { + .mode_str = "480x272", + .default_bpp = 24, +}; + +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ +} +/* + * Not defined the cd/wp so far, set it always present for debug*/ +static const struct esdhc_platform_data mvfa5_sd1_data __initconst = { + .cd_gpio = MVF600_SD1_CD, + .wp_gpio = -1, +}; + +static struct imxi2c_platform_data mvf600_i2c_data = { + .bitrate = 100000, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + I2C_BOARD_INFO("sgtl5000", 0x0a), + }, +}; + +static struct mxc_nand_platform_data mvf_data __initdata = { + .width = 2, +}; + +static void __init mvf_twr_init_usb(void) +{ + imx_otg_base = MVF_IO_ADDRESS(MVF_USBC0_BASE_ADDR); + /*mvf_set_otghost_vbus_func(mvf_twr_usbotg_vbus);*/ +#ifdef CONFIG_USB_GADGET_ARC + mvf_usb_dr_init(); +#endif +#ifdef CONFIG_USB_EHCI_ARC + mvf_usb_dr2_init(); +#endif +} + +/*! + * Board specific initialization. + */ +static void __init mvf_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mvf600_pads, + ARRAY_SIZE(mvf600_pads)); + mvf_vf700_init_uart(); + + mvf_init_fec(fec_data); + + mvf_add_snvs_rtc(); + + mvf_add_sdhci_esdhc_imx(1, &mvfa5_sd1_data); + + mvf_add_imx_i2c(0, &mvf600_i2c_data); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); +#if 0 + mvf_add_dspi(0, &mvf_vf700_spi_data); + spi_device_init(); +#endif + mvfa5_add_dcu(0, &mvf_dcu_pdata); + + mxc_register_device(&mvf_twr_audio_device, &mvf_twr_audio_data); + mvfa5_add_sai(2, &mvf_sai_pdata); + + mvf_twr_init_usb(); + + mvf_add_nand(&mvf_data); +} + +static void __init mvf_timer_init(void) +{ +#if 0 + struct clk *uart_clk; + uart_clk = clk_get_sys("mvf-uart.0", NULL); + early_console_setup(MVF_UART1_BASE_ADDR, uart_clk); +#endif + mvf_clocks_init(32768, 24000000, 0, 0); +} + +static struct sys_timer mxc_timer = { + .init = mvf_timer_init, +}; + +/* + * initialize __mach_desc_ data structure. + */ +MACHINE_START(MVFA5_TWR_VF700, "Freescale MVF TOWER VF700 Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .boot_params = MVF_PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mvf_map_io, + .init_irq = mvf_init_irq, + .init_machine = mvf_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mvf/bus_freq.c b/arch/arm/mach-mvf/bus_freq.c new file mode 100644 index 000000000000..1bf5ea9df216 --- /dev/null +++ b/arch/arm/mach-mvf/bus_freq.c @@ -0,0 +1,65 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * + * Dummy API for the Freescale Semiconductor MVF CPUfreq module + * and DVFS CORE module. + * + */ +#include <asm/io.h> +#include <linux/sched.h> +#include <linux/proc_fs.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/mutex.h> +#include <mach/iram.h> +#include <mach/hardware.h> +#include <mach/clock.h> +#include <mach/mxc_dvfs.h> +#include <mach/sdram_autogating.h> +#include <asm/mach/map.h> +#include <asm/mach-types.h> +#include <asm/cacheflush.h> +#include <asm/tlb.h> + +int high_bus_freq_mode; +int med_bus_freq_mode; +int low_bus_freq_mode; + +int set_low_bus_freq(void) +{ + return 0; +} + +int set_high_bus_freq(int high_bus_freq) +{ + return 0; +} + +void set_ddr_freq(int ddr_rate) +{ + +} + +int low_freq_bus_used(void) +{ + return 0; +} diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c new file mode 100644 index 000000000000..88d60c1e5e07 --- /dev/null +++ b/arch/arm/mach-mvf/clock.c @@ -0,0 +1,1740 @@ + +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/time.h> +#include <linux/hrtimer.h> +#include <linux/mm.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/clkdev.h> +#include <linux/regulator/consumer.h> +#include <asm/div64.h> +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/clock.h> +#include <mach/mxc_dvfs.h> +#include "crm_regs.h" +#include "regs-anadig.h" + +#ifdef CONFIG_CLK_DEBUG +#define __INIT_CLK_DEBUG(n) .name = #n, +#else +#define __INIT_CLK_DEBUG(n) +#endif + + +void __iomem *apll_base; +static struct clk pll1_sys_main_clk; +static struct clk pll2_528_bus_main_clk; +static struct clk pll2_pfd2_452M; +static struct clk pll3_usb_otg_main_clk; +static struct clk pll4_audio_main_clk; +static struct clk pll6_video_main_clk; +static struct clk pll5_enet_main_clk; +static struct clk pll1_pfd3_396M; + +unsigned long arm_core_clk = 396000000; /* cpu core clk, up to 452MHZ */ +unsigned long arm_sys_clk = 396000000; /* ARM_CLK_DIV, system bus clock */ +unsigned long platform_bus_clk = 132000000; /* BUS_CLK_DIV, up to 166MHZ */ +unsigned long ipg_bus_clk = 66000000; /* IPS clk */ + +#define SPIN_DELAY 1200000 /* in nanoseconds */ + +#define AUDIO_VIDEO_MIN_CLK_FREQ 650000000 +#define AUDIO_VIDEO_MAX_CLK_FREQ 1300000000 + +/* We need to check the exp status again after timer expiration, + * as there might be interrupt coming between the first time exp + * and the time reading, then the time reading may be several ms + * after the exp checking due to the irq handle, so we need to + * check it to make sure the exp return the right value after + * timer expiration. */ +#define WAIT(exp, timeout) \ +({ \ + struct timespec nstimeofday; \ + struct timespec curtime; \ + int result = 1; \ + getnstimeofday(&nstimeofday); \ + while (!(exp)) { \ + getnstimeofday(&curtime); \ + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \ + if (!(exp)) \ + result = 0; \ + break; \ + } \ + } \ + result; \ +}) + +/* External clock values passed-in by the board code */ +static unsigned long external_high_reference, external_low_reference; +static unsigned long oscillator_reference, ckih2_reference; +static unsigned long anaclk_1_reference, anaclk_2_reference; + + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +/* Clock off in all modes */ +static void _clk_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + +} + +/* Clock off in wait mode */ +static void _clk_disable_inwait(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +/* + * For the 5-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, + struct clk *m3, struct clk *m4) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else if (parent == m4) + return 4; + else + BUG(); + + return 0; +} + +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_sys_main_clk) + return PLL1_SYS_BASE_ADDR; + else if (pll == &pll2_528_bus_main_clk) + return PLL2_528_BASE_ADDR; + else if (pll == &pll3_usb_otg_main_clk) + return PLL3_480_USB1_BASE_ADDR; + else if (pll == &pll4_audio_main_clk) + return PLL4_AUDIO_BASE_ADDR; + else if (pll == &pll5_enet_main_clk) + return PLL5_ENET_BASE_ADDR; + else if (pll == &pll6_video_main_clk) + return PLL6_VIDEO_BASE_ADDR; + else if (pll == &pll1_pfd3_396M) + return PLL1_SYS_BASE_ADDR; + else + BUG(); + return NULL; +} + + +/* + * For the 6-to-1 muxed input clock + */ +static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1, + struct clk *m2, struct clk *m3, struct clk *m4, + struct clk *m5) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else if (parent == m4) + return 4; + else if (parent == m5) + return 5; + else + BUG(); + + return 0; +} +static unsigned long get_high_reference_clock_rate(struct clk *clk) +{ + return external_high_reference; +} + +static unsigned long get_low_reference_clock_rate(struct clk *clk) +{ + return external_low_reference; +} + +static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) +{ + return oscillator_reference; +} + +static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) +{ + return ckih2_reference; +} + +static unsigned long _clk_anaclk_1_get_rate(struct clk *clk) +{ + return anaclk_1_reference; +} + +static int _clk_anaclk_1_set_rate(struct clk *clk, unsigned long rate) +{ + anaclk_1_reference = rate; + return 0; +} + +static unsigned long _clk_anaclk_2_get_rate(struct clk *clk) +{ + return anaclk_2_reference; +} + +static int _clk_anaclk_2_set_rate(struct clk *clk, unsigned long rate) +{ + anaclk_2_reference = rate; + return 0; +} + +/* External high frequency clock */ +static struct clk ckih_clk = { + __INIT_CLK_DEBUG(ckih_clk) + .get_rate = get_high_reference_clock_rate, +}; + +static struct clk ckih2_clk = { + __INIT_CLK_DEBUG(ckih2_clk) + .get_rate = get_ckih2_reference_clock_rate, +}; + +static struct clk osc_clk = { + __INIT_CLK_DEBUG(osc_clk) + .get_rate = get_oscillator_reference_clock_rate, +}; + +/* External low frequency (32kHz) clock */ +static struct clk ckil_clk = { + __INIT_CLK_DEBUG(ckil_clk) + .get_rate = get_low_reference_clock_rate, +}; + +static struct clk anaclk_1 = { + __INIT_CLK_DEBUG(anaclk_1) + .get_rate = _clk_anaclk_1_get_rate, + .set_rate = _clk_anaclk_1_set_rate, +}; + +static struct clk anaclk_2 = { + __INIT_CLK_DEBUG(anaclk_2) + .get_rate = _clk_anaclk_2_get_rate, + .set_rate = _clk_anaclk_2_set_rate, +}; + +static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate) +{ + u32 frac; + u64 tmp; + + tmp = (u64)clk_get_rate(clk->parent) * 18; + tmp += rate/2; + do_div(tmp, rate); + frac = tmp; + frac = frac < 12 ? 12 : frac; + frac = frac > 35 ? 35 : frac; + tmp = (u64)clk_get_rate(clk->parent) * 18; + do_div(tmp, frac); + return tmp; +} + +static unsigned long pfd_get_rate(struct clk *clk) +{ + u32 frac; + u64 tmp; + tmp = (u64)clk_get_rate(clk->parent) * 18; + + + frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) & + ANADIG_PFD_FRAC_MASK; + + do_div(tmp, frac); + + return tmp; +} + +static int pfd_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, frac; + u64 tmp; + tmp = (u64)clk_get_rate(clk->parent) * 18; + + + /* Round up the divider so that we don't set a rate + * higher than what is requested. */ + tmp += rate/2; + do_div(tmp, rate); + frac = tmp; + frac = frac < 12 ? 12 : frac; + frac = frac > 35 ? 35 : frac; + /* clear clk frac bits */ + reg = __raw_readl(clk->enable_reg); + reg &= ~(ANADIG_PFD_FRAC_MASK << clk->enable_shift); + /* set clk frac bits */ + __raw_writel(reg | (frac << clk->enable_shift), + clk->enable_reg); + + return 0; +} + +static int _clk_pfd_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + /* clear clk gate bit */ + __raw_writel(reg & ~(1 << (clk->enable_shift + 7)), + clk->enable_reg); + + return 0; +} + +static void _clk_pfd_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + /* set clk gate bit */ + __raw_writel(reg | (1 << (clk->enable_shift + 7)), + clk->enable_reg); + +} + +static int _clk_pll_enable(struct clk *clk) +{ + unsigned int reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + + reg = __raw_readl(pllbase); + reg &= ~ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_POWER_DOWN; + + /* The 480MHz PLLs have the opposite definition for power bit. */ + if (clk == &pll3_usb_otg_main_clk) + reg |= (ANADIG_PLL_POWER_DOWN|ANADIG_PLL_480_EN_USB_CLKS); + + __raw_writel(reg, pllbase); + + /* Wait for PLL to lock */ + if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK, + SPIN_DELAY)) + panic("pll enable failed\n"); + + /* Enable the PLL output now*/ + reg = __raw_readl(pllbase); + reg |= ANADIG_PLL_ENABLE; + __raw_writel(reg, pllbase); + + if (clk == &pll3_usb_otg_main_clk) { + /* config OTG2 PLL CLK*/ + reg = __raw_readl(PLL3_480_USB2_BASE_ADDR); + reg &= ~ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_POWER_DOWN; + reg |= (ANADIG_PLL_POWER_DOWN|ANADIG_PLL_480_EN_USB_CLKS); + + __raw_writel(reg, PLL3_480_USB2_BASE_ADDR); + + if (!WAIT(__raw_readl(PLL3_480_USB2_BASE_ADDR) & + ANADIG_PLL_LOCK, SPIN_DELAY)) + panic("pll enable failed\n"); + + reg = __raw_readl(PLL3_480_USB2_BASE_ADDR); + reg |= ANADIG_PLL_ENABLE; + __raw_writel(reg, PLL3_480_USB2_BASE_ADDR); + } + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + unsigned int reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + + reg = __raw_readl(pllbase); + reg |= ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_ENABLE; + + __raw_writel(reg, pllbase); + +} + +/* PLL sys: 528 or 480 MHz*/ +static unsigned long _clk_pll1_main_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + /* div_sel: 0 -> Fout = Fref x 20; 1 -> Fout = Fref x 22 */ + div = __raw_readl(PLL1_SYS_BASE_ADDR) & 0x1; + val = (clk_get_rate(clk->parent) * (div ? 22 : 20)); + return val; +} + +static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + div = (rate) / clk_get_rate(clk->parent); + + /* Update div */ + reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~0x1; + + reg |= ((div > 20) ? 1 : 0); + __raw_writel(reg, PLL1_SYS_BASE_ADDR); + + /* Wait for PLL1 to lock */ + if (!WAIT(__raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_LOCK, + SPIN_DELAY)) + panic("pll1 enable failed\n"); + + return 0; +} + +static unsigned long _clk_pll1_pfd2_get_rate(struct clk *clk) +{ + return 452000000; +} + +static int _clk_pll1_pfd2_set_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} + +static unsigned long _clk_pll1_pfd3_get_rate(struct clk *clk) +{ + return 396000000; +} + +static int _clk_pll1_pfd3_set_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} + +static struct clk pll1_sys_main_clk = { + __INIT_CLK_DEBUG(pll1_sys_main_clk) + .parent = &osc_clk, + .get_rate = _clk_pll1_main_get_rate, + .set_rate = _clk_pll1_main_set_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static struct clk pll1_pfd2_452M = { + __INIT_CLK_DEBUG(pll1_pfd2_452M) + .parent = &osc_clk, + .enable_reg = (void *)PFD_528SYS_BASE_ADDR, + .enable_shift = ANADIG_PFD1_FRAC_OFFSET, + .get_rate = _clk_pll1_pfd2_get_rate, + .set_rate = _clk_pll1_pfd2_set_rate, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, +}; + +static struct clk pll1_pfd3_396M = { + __INIT_CLK_DEBUG(pll1_pfd3_396M) + .parent = &osc_clk, + .enable_reg = (void *)PFD_528SYS_BASE_ADDR, + .enable_shift = ANADIG_PFD2_FRAC_OFFSET, + .get_rate = _clk_pll1_pfd3_get_rate, + .set_rate = _clk_pll1_pfd3_set_rate, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, +}; + +/* + * PLL PFD output select + * CCM Clock Switcher Register + */ +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCSR); + /* enable PLL1 PFD */ + reg |= 0xf00; + + if (parent == &pll1_sys_main_clk) { + reg &= ~MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; + + } else if (parent == &pll1_pfd2_452M) { + reg &= ~MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; + reg |= (0x2 << MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET); + + } else if (parent == &pll1_pfd3_396M) { + reg &= ~MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; + reg |= (0x3 << MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET); + + } + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +static unsigned long _clk_pll1_sw_get_rate(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_CCSR); + reg &= MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; + reg = (reg >> MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET); + + if (reg == 0x1) + return 500000000; + else if (reg == 0x2) + return 452000000; + else if (reg == 0x3) + return 396000000; + else + return 528000000; + +} + +static struct clk pll1_sw_clk = { + __INIT_CLK_DEBUG(pll1_sw_clk) + .parent = &pll1_sys_main_clk, + .set_parent = _clk_pll1_sw_set_parent, + .get_rate = _clk_pll1_sw_get_rate, +}; + +static unsigned long _clk_pll2_main_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT; + + if (div == 1) + val = clk_get_rate(clk->parent) * 22; + + else + val = clk_get_rate(clk->parent) * 20; + + return val; +} + +static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + if (rate == 528000000) + div = 1; + else if (rate == 480000000) + div = 0; + else + return -EINVAL; + + reg = __raw_readl(PLL2_528_BASE_ADDR); + reg &= ~ANADIG_PLL_528_DIV_SELECT; + reg |= div; + __raw_writel(reg, PLL2_528_BASE_ADDR); + + return 0; +} + +static struct clk pll2_528_bus_main_clk = { + __INIT_CLK_DEBUG(pll2_528_bus_main_clk) + .parent = &osc_clk, + .get_rate = _clk_pll2_main_get_rate, + .set_rate = _clk_pll2_main_set_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static struct clk pll2_pfd2_396M = { + __INIT_CLK_DEBUG(pll2_pfd_396M) + .parent = &pll2_528_bus_main_clk, + .enable_reg = (void *)PFD_528_BASE_ADDR, + .enable_shift = BP_ANADIG_PFD_528_PFD1_FRAC, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .get_rate = pfd_get_rate, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll2_pfd3_339M = { + __INIT_CLK_DEBUG(pll2_pfd_339M) + .parent = &pll2_528_bus_main_clk, + .enable_reg = (void *)PFD_528_BASE_ADDR, + .enable_shift = BP_ANADIG_PFD_528_PFD2_FRAC, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll2_pfd4_413M = { + __INIT_CLK_DEBUG(pll2_pfd_413M) + .parent = &pll2_528_bus_main_clk, + .enable_reg = (void *)PFD_528_BASE_ADDR, + .enable_shift = BP_ANADIG_PFD_528_PFD3_FRAC, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(PLL3_480_USB1_BASE_ADDR) + & ANADIG_PLL_480_DIV_SELECT_MASK; + + if (div == 1) + val = clk_get_rate(clk->parent) * 22; + else + val = clk_get_rate(clk->parent) * 20; + return val; +} + +static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + if (rate == 528000000) + div = 1; + else if (rate == 480000000) + div = 0; + else + return -EINVAL; + + reg = __raw_readl(PLL3_480_USB1_BASE_ADDR); + reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK; + reg |= div; + __raw_writel(reg, PLL3_480_USB1_BASE_ADDR); + + return 0; +} + + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_usb_otg_main_clk = { + __INIT_CLK_DEBUG(pll3_usb_otg_main_clk) + .parent = &osc_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_pll3_usb_otg_set_rate, + .get_rate = _clk_pll3_usb_otg_get_rate, +}; + +static unsigned long _clk_usb_get_rate(struct clk *clk) +{ + return 60000000; +} + +static struct clk usb_clk = { + __INIT_CLK_DEBUG(usb_clk) + .get_rate = _clk_usb_get_rate, +}; + +/* for USB OTG1 */ +static struct clk usb_phy0_clk = { + __INIT_CLK_DEBUG(usb_phy0_clk) + .parent = &pll3_usb_otg_main_clk, + .set_rate = _clk_pll3_usb_otg_set_rate, + .get_rate = _clk_pll3_usb_otg_get_rate, +}; + +/* For USB OTG2 */ +static struct clk usb_phy1_clk = { + __INIT_CLK_DEBUG(usb_phy1_clk) + .parent = &pll3_usb_otg_main_clk, + .set_rate = _clk_pll3_usb_otg_set_rate, + .get_rate = _clk_pll3_usb_otg_get_rate, +}; + + +static struct clk pll3_pfd2_396M = { + __INIT_CLK_DEBUG(pll3_pfd2_396M) + .parent = &pll3_usb_otg_main_clk, + .enable_reg = (void *)PFD_480_BASE_ADDR, + .enable_shift = BP_ANADIG_PFD_480_PFD1_FRAC, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll3_pfd3_308M = { + __INIT_CLK_DEBUG(pll3_pfd3_309M) + .parent = &pll3_usb_otg_main_clk, + .enable_reg = (void *)PFD_480_BASE_ADDR, + .enable_shift = BP_ANADIG_PFD_480_PFD2_FRAC, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll3_pfd4_320M = { + __INIT_CLK_DEBUG(pll3_pfd4_320M) + .parent = &pll3_usb_otg_main_clk, + .enable_reg = (void *)PFD_480_BASE_ADDR, + .enable_shift = BP_ANADIG_PFD_480_PFD3_FRAC, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static unsigned long _clk_pll3_sw_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent); +} + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_sw_clk = { + __INIT_CLK_DEBUG(pll3_sw_clk) + .parent = &pll3_usb_otg_main_clk, + .get_rate = _clk_pll3_sw_get_rate, +}; +/* +*/ + +static unsigned long _clk_audio_video_get_rate(struct clk *clk) +{ + unsigned int div, mfn, mfd; + unsigned long rate; + unsigned int parent_rate = clk_get_rate(clk->parent); + void __iomem *pllbase; + + unsigned int test_div_sel, control3, post_div = 1; + + if (clk == &pll4_audio_main_clk) + pllbase = PLL4_AUDIO_BASE_ADDR; + else + pllbase = PLL6_VIDEO_BASE_ADDR; + + + div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK; + mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET); + mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET); + + rate = (parent_rate * div) + ((parent_rate / mfd) * mfn); + rate = rate / post_div; + + return rate; +} + +static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + unsigned int mfn, mfd = 1000000; + s64 temp64; + unsigned int parent_rate = clk_get_rate(clk->parent); + void __iomem *pllbase; + unsigned long min_clk_rate, pre_div_rate; + + u32 test_div_sel = 2; + u32 control3 = 0; + + + if (clk == &pll4_audio_main_clk) + min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4; + else + min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16; + + if ((rate < min_clk_rate) || (rate > AUDIO_VIDEO_MAX_CLK_FREQ)) + return -EINVAL; + + if (clk == &pll4_audio_main_clk) + pllbase = PLL4_AUDIO_BASE_ADDR; + else + pllbase = PLL6_VIDEO_BASE_ADDR; + + pre_div_rate = rate; + div = pre_div_rate / parent_rate; + temp64 = (u64) (pre_div_rate - (div * parent_rate)); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + reg = __raw_readl(pllbase) + & ~ANADIG_PLL_SYS_DIV_SELECT_MASK + & ~ANADIG_PLL_AV_TEST_DIV_SEL_MASK; + reg |= div | + (test_div_sel << ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET); + __raw_writel(reg, pllbase); + __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET); + __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET); + + return 0; +} + +static unsigned long _clk_audio_video_round_rate(struct clk *clk, + unsigned long rate) +{ + unsigned long min_clk_rate; + unsigned int div, post_div = 1; + unsigned int mfn, mfd = 1000000; + s64 temp64; + unsigned int parent_rate = clk_get_rate(clk->parent); + unsigned long pre_div_rate; + u32 test_div_sel = 2; + u32 control3 = 0; + unsigned long final_rate; + + if (clk == &pll4_audio_main_clk) + min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4; + else + min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16; + + if (rate < min_clk_rate) + return min_clk_rate; + + if (rate > AUDIO_VIDEO_MAX_CLK_FREQ) + return AUDIO_VIDEO_MAX_CLK_FREQ; + + pre_div_rate = rate; + + div = pre_div_rate / parent_rate; + temp64 = (u64) (pre_div_rate - (div * parent_rate)); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + final_rate = (parent_rate * div) + ((parent_rate / mfd) * mfn); + final_rate = final_rate / post_div; + + return final_rate; +} + +static int _clk_audio_video_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + void __iomem *pllbase; + + if (clk == &pll4_audio_main_clk) + pllbase = PLL4_AUDIO_BASE_ADDR; + else + pllbase = PLL6_VIDEO_BASE_ADDR; +#if 0 + reg = __raw_readl(pllbase) & ~ANADIG_PLL_BYPASS_CLK_SRC_MASK; + mux = _get_mux6(parent, &osc_clk, &anaclk_1, &anaclk_2, + NULL, NULL, NULL); + reg |= mux << ANADIG_PLL_BYPASS_CLK_SRC_OFFSET; + __raw_writel(reg, pllbase); + + /* Set anaclk_x as input */ + if (parent == &anaclk_1) { + reg = __raw_readl(ANADIG_MISC1_REG); + reg |= (ANATOP_LVDS_CLK1_IBEN_MASK & + ~ANATOP_LVDS_CLK1_OBEN_MASK); + __raw_writel(reg, ANADIG_MISC1_REG); + } else if (parent == &anaclk_2) { + reg = __raw_readl(ANADIG_MISC1_REG); + reg |= (ANATOP_LVDS_CLK2_IBEN_MASK & + ~ANATOP_LVDS_CLK2_OBEN_MASK); + __raw_writel(reg, ANADIG_MISC1_REG); + } +#endif + return 0; +} + +static struct clk pll4_audio_main_clk = { + __INIT_CLK_DEBUG(pll4_audio_main_clk) + .parent = &osc_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_audio_video_set_rate, + .get_rate = _clk_audio_video_get_rate, + .round_rate = _clk_audio_video_round_rate, + .set_parent = _clk_audio_video_set_parent, +}; + +static struct clk pll6_video_main_clk = { + __INIT_CLK_DEBUG(pll6_video_main_clk) + .parent = &osc_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_audio_video_set_rate, + .get_rate = _clk_audio_video_get_rate, + .round_rate = _clk_audio_video_round_rate, + .set_parent = _clk_audio_video_set_parent, +}; + + +static struct clk pll5_enet_main_clk = { + __INIT_CLK_DEBUG(pll5_enet_main_clk) + .parent = &osc_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static unsigned long _clk_arm_get_rate(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = (cacrr & MXC_CCM_CACRR_ARM_CLK_DIV_MASK) + 1; + return arm_core_clk; + /*return clk_get_rate(clk->parent) / div;*/ +} + +static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_CCSR); + reg |= (1 << MXC_CCM_CCSR_CA5_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + + +static struct clk cpu_clk = { + __INIT_CLK_DEBUG(cpu_clk) + .parent = &pll1_sw_clk, /* A5 clock from PLL1 pfd3 out 396MHZ */ + .set_rate = _clk_arm_set_rate, + .get_rate = _clk_arm_get_rate, +}; +/* +*/ + +/* platform bus clock parent, CCM_CCSR.SYS_CLK_SEL */ +static int _clk_periph_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + mux = _get_mux6(parent, &ckih_clk, &ckil_clk, + &pll2_pfd2_396M, &pll2_528_bus_main_clk, + &pll1_pfd3_396M, &pll3_usb_otg_main_clk); + + reg = __raw_readl(MXC_CCM_CCSR); + /* */ + reg &= ~MXC_CCM_CCSR_SYS_CLK_SEL_MASK; + reg |= mux; + __raw_writel(reg, MXC_CCM_CCSR); + + /* + * Set the BUS_CLK_DIV to 3, 396/3=132 + * Set IPG_CLK_DIV to 2, 132/2=66 + */ + reg = __raw_readl(MXC_CCM_CACRR); + reg &= ~MXC_CCM_CACRR_BUS_CLK_DIV_MASK; + reg &= ~MXC_CCM_CACRR_IPG_CLK_DIV_MASK; + reg |= (2 << MXC_CCM_CACRR_BUS_CLK_DIV_OFFSET); + reg |= (1 << MXC_CCM_CACRR_IPG_CLK_DIV_OFFSET); + __raw_writel(reg, MXC_CCM_CACRR); + + return 0; +} + +static unsigned long _clk_periph_get_rate(struct clk *clk) +{ + unsigned long val = 132000000; + return val; +} + +static struct clk periph_clk = { + __INIT_CLK_DEBUG(periph_clk) + .parent = &pll2_pfd2_396M, + .set_parent = _clk_periph_set_parent, + .get_rate = _clk_periph_get_rate, +}; + + + +static unsigned long _clk_ipg_get_rate(struct clk *clk) +{ + return 66000000; +} + + +static struct clk ipg_clk = { + __INIT_CLK_DEBUG(ipg_clk) + .parent = &periph_clk, + .get_rate = _clk_ipg_get_rate, +}; + + +static int _clk_enet_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg = __raw_readl(MXC_CCM_CSCMR2) + & ~MXC_CCM_CSCMR2_RMII_CLK_SEL_MASK; + + mux = _get_mux6(parent, NULL, NULL, &pll5_enet_main_clk, + NULL, NULL, NULL); + + reg |= (mux << MXC_CCM_CSCMR2_RMII_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static int _clk_enet_enable(struct clk *clk) +{ + unsigned int reg; + + /* Enable ENET ref clock */ + reg = __raw_readl(PLL5_ENET_BASE_ADDR); + reg &= ~ANADIG_PLL_BYPASS; + reg |= ANADIG_PLL_ENABLE; + __raw_writel(reg, PLL5_ENET_BASE_ADDR); + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg |= MXC_CCM_CSCDR1_RMII_CLK_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); + + _clk_enable(clk); + return 0; +} + +static void _clk_enet_disable(struct clk *clk) +{ + unsigned int reg; + + _clk_disable(clk); + + /* Enable ENET ref clock */ + reg = __raw_readl(PLL5_ENET_BASE_ADDR); + reg |= ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_ENABLE; + __raw_writel(reg, PLL5_ENET_BASE_ADDR); +} + +static int _clk_enet_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div = 1; + + switch (rate) { + case 25000000: + div = 0; + break; + case 50000000: + div = 1; + break; + case 100000000: + div = 2; + break; + case 125000000: + div = 3; + break; + default: + return -EINVAL; + } + reg = __raw_readl(PLL5_ENET_BASE_ADDR); + reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK; + reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET); + __raw_writel(reg, PLL5_ENET_BASE_ADDR); + + return 0; +} + +static unsigned long _clk_enet_get_rate(struct clk *clk) +{ + unsigned int div; + + div = (__raw_readl(PLL5_ENET_BASE_ADDR)) + & ANADIG_PLL_ENET_DIV_SELECT_MASK; + + switch (div) { + case 0: + div = 20; + break; + case 1: + div = 10; + break; + case 3: + div = 5; + break; + case 4: + div = 4; + break; + } + + return 500000000 / div; +} + +static struct clk enet_clk[] = { + { + __INIT_CLK_DEBUG(enet_clk) + .id = 0, + .parent = &pll5_enet_main_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .set_parent = _clk_enet_set_parent, + .enable = _clk_enet_enable, + .disable = _clk_enet_disable, + .set_rate = _clk_enet_set_rate, + .get_rate = _clk_enet_get_rate, + .secondary = &enet_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, +}; + + + +static unsigned long _clk_uart_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 64) + div = 64; + + return parent_rate / div; +} +/* +*/ +static unsigned long _clk_uart_get_rate(struct clk *clk) +{ + + return clk_get_rate(clk->parent); +} + +static struct clk uart_clk[] = { + { + __INIT_CLK_DEBUG(uart_clk) + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &uart_clk[1], + .get_rate = _clk_uart_get_rate, + .round_rate = _clk_uart_round_rate, + }, + { + __INIT_CLK_DEBUG(uart_serial_clk) + .id = 1, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk dspi_clk[] = { + { + __INIT_CLK_DEBUG(dspi0_clk) + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg = __raw_readl(MXC_CCM_CSCMR1) + & ~MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll3_usb_otg_main_clk, &pll3_pfd3_308M, + &pll1_pfd3_396M, NULL, NULL, NULL); + + reg |= (mux << MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_esdhc1_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR2); + div = ((reg & MXC_CCM_CSCDR2_ESDHC1_DIV_MASK) >> + MXC_CCM_CSCDR2_ESDHC1_DIV_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_esdhc1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = (parent_rate + rate - 1) / rate; + if (div == 0) + div++; + if (((parent_rate / div) > rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR2); + reg &= ~MXC_CCM_CSCDR2_ESDHC1_DIV_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR2_ESDHC1_DIV_OFFSET; + reg |= MXC_CCM_CSCDR2_ESDHC1_EN; + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; +} + +static unsigned long _clk_esdhc_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static struct clk esdhc1_clk = { + __INIT_CLK_DEBUG(esdhc1_clk) + .id = 1, + .parent = &pll1_pfd3_396M, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_esdhc1_set_parent, + .round_rate = _clk_esdhc_round_rate, + .set_rate = _clk_esdhc1_set_rate, + .get_rate = _clk_esdhc1_get_rate, +}; + +static int _clk_dcu0_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg = __raw_readl(MXC_CCM_CSCMR1) + & ~MXC_CCM_CSCMR1_DCU0_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll1_pfd2_452M, &pll3_usb_otg_main_clk, + NULL, NULL, NULL, NULL); + + reg |= (mux << MXC_CCM_CSCMR1_DCU0_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static int _clk_dcu_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR3); + reg |= MXC_CCM_CSCDR3_DCU0_EN; + __raw_writel(reg, MXC_CCM_CSCDR3); + + return 0; +} + +static void _clk_dcu_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR3); + reg &= ~MXC_CCM_CSCDR3_DCU0_EN; + __raw_writel(reg, MXC_CCM_CSCDR3); + + return 0; +} + +static unsigned long _clk_dcu0_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR3); + div = ((reg & MXC_CCM_CSCDR3_DCU0_DIV_MASK) >> + MXC_CCM_CSCDR3_DCU0_DIV_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_dcu0_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = (parent_rate + rate - 1) / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR3); + reg &= ~MXC_CCM_CSCDR3_DCU0_DIV_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR3_DCU0_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR3); + + return 0; +} + +static unsigned long _clk_dcu0_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static struct clk dcu0_clk = { + __INIT_CLK_DEBUG(dcu0_clk) + .parent = &pll1_pfd2_452M, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_dcu_enable, + .disable = _clk_dcu_disable, + .set_parent = _clk_dcu0_set_parent, + .round_rate = _clk_dcu0_round_rate, + .set_rate = _clk_dcu0_set_rate, + .get_rate = _clk_dcu0_get_rate, +}; + +static unsigned long get_audio_external_clock_rate(struct clk *clk) +{ + return 24576000; +} + +static struct clk audio_external_clk = { + __INIT_CLK_DEBUG(audio_external_clk) + .get_rate = get_audio_external_clock_rate, +}; + +static int _clk_sai2_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg = __raw_readl(MXC_CCM_CSCMR1) + & ~MXC_CCM_CSCMR1_SAI2_CLK_SEL_MASK; + + mux = _get_mux6(parent, &audio_external_clk, NULL, + NULL, &pll4_audio_main_clk, NULL, NULL); + + reg |= (mux << MXC_CCM_CSCMR1_SAI2_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_sai2_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = ((reg & MXC_CCM_CSCDR1_SAI2_DIV_MASK) >> + MXC_CCM_CSCDR1_SAI2_DIV_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_sai2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 16)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_SAI2_DIV_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR1_SAI2_DIV_OFFSET; + reg |= MXC_CCM_CSCDR1_SAI2_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static int _clk_sai2_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg |= MXC_CCM_CSCDR1_SAI2_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static void _clk_sai2_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_SAI2_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static unsigned long _clk_sai_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static struct clk sai2_clk = { + __INIT_CLK_DEBUG(sai2_clk) + .parent = &audio_external_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_sai2_enable, + .disable = _clk_sai2_disable, + .set_parent = _clk_sai2_set_parent, + .round_rate = _clk_sai_round_rate, + .set_rate = _clk_sai2_set_rate, + .get_rate = _clk_sai2_get_rate, +}; + +static int _clk_enable1(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_disable1(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, reg; + + if (parent == &pll3_usb_otg_main_clk) + sel = 0; + else if (parent == &pll2_528_bus_main_clk) + sel = 1; + else if (parent == &pll1_sys_main_clk) + sel = 2; + else if (parent == &pll6_video_main_clk) + sel = 3; + else if (parent == &pll4_audio_main_clk) + sel = 15; + else + return -EINVAL; + return 0; +} + +static unsigned long _clk_clko_get_rate(struct clk *clk) +{ + return 0; +} + +static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + return 0; +} + +static unsigned long _clk_clko_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (div > 8) + div = 8; + return parent_rate / div; +} + +static int _clk_clko2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, reg; + return 0; +} + +static unsigned long _clk_clko2_get_rate(struct clk *clk) +{ + return 0; +} + +static int _clk_clko2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + return 0; +} + +static struct clk clko_clk = { + __INIT_CLK_DEBUG(clko_clk) + .parent = &pll2_528_bus_main_clk, + .enable = _clk_enable1, + .disable = _clk_disable1, + .set_parent = _clk_clko_set_parent, + .set_rate = _clk_clko_set_rate, + .get_rate = _clk_clko_get_rate, + .round_rate = _clk_clko_round_rate, +}; + +static struct clk clko2_clk = { + __INIT_CLK_DEBUG(clko2_clk) + .enable = _clk_enable1, + .disable = _clk_disable1, + .set_parent = _clk_clko2_set_parent, + .set_rate = _clk_clko2_set_rate, + .get_rate = _clk_clko2_get_rate, + .round_rate = _clk_clko_round_rate, +}; + +static struct clk pit_clk = { + __INIT_CLK_DEBUG(pit_clk) + .parent = &ipg_clk, +#if 0 + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#endif + .get_rate = _clk_uart_get_rate, +}; + +static struct clk i2c_clk[] = { + { + __INIT_CLK_DEBUG(i2c_clk_0) + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk dummy_clk = { + .id = 0, +}; + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + } + + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK(NULL, "osc", osc_clk), + _REGISTER_CLOCK(NULL, "ckih", ckih_clk), + _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk), + _REGISTER_CLOCK(NULL, "ckil", ckil_clk), + _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk), + _REGISTER_CLOCK(NULL, "pll1_pfd2_452M", pll1_pfd2_452M), + _REGISTER_CLOCK(NULL, "pll1_pfd3_396M", pll1_pfd3_396M), + _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk), /*PLL1 pfd out clk*/ + _REGISTER_CLOCK(NULL, "pll2_main_clk", pll2_528_bus_main_clk), + _REGISTER_CLOCK(NULL, "pll2_pfd2_396M", pll2_pfd2_396M), + _REGISTER_CLOCK(NULL, "pll2_pfd3_339M", pll2_pfd3_339M), + _REGISTER_CLOCK(NULL, "pll2_pfd4_413M", pll2_pfd4_413M), + _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk), + _REGISTER_CLOCK(NULL, "pll3_pfd2_396M", pll3_pfd2_396M), + _REGISTER_CLOCK(NULL, "pll3_pfd3_308M", pll3_pfd3_308M), + _REGISTER_CLOCK(NULL, "pll3_pfd4_320M", pll3_pfd4_320M), + _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk), + _REGISTER_CLOCK(NULL, "pll5", pll6_video_main_clk), + _REGISTER_CLOCK(NULL, "pll6", pll5_enet_main_clk), + _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk), /* arm core clk */ + _REGISTER_CLOCK(NULL, "periph_clk", periph_clk), /* platform bus clk */ + _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk), + _REGISTER_CLOCK(NULL, "audio ext clk", audio_external_clk), + _REGISTER_CLOCK(NULL, "mvf-uart.0", uart_clk[0]), + _REGISTER_CLOCK(NULL, "mvf-uart.1", uart_clk[0]), + _REGISTER_CLOCK(NULL, "mvf-uart.2", uart_clk[0]), + _REGISTER_CLOCK(NULL, "mvf-uart.3", uart_clk[0]), + _REGISTER_CLOCK("mvf-dspi.0", NULL, dspi_clk[0]), + _REGISTER_CLOCK("pit", NULL, pit_clk), + _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]), + _REGISTER_CLOCK("mvf-wdt.0", NULL, dummy_clk), + _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc1_clk), + _REGISTER_CLOCK("mvf-dcu.0", NULL, dcu0_clk), + _REGISTER_CLOCK("mvf-sai.0", NULL, sai2_clk), + _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]), + _REGISTER_CLOCK(NULL, "usb-clk", usb_clk), + _REGISTER_CLOCK(NULL, "mvf-usb.0", usb_phy0_clk), + _REGISTER_CLOCK(NULL, "mvf-usb.1", usb_phy1_clk), +}; + +static void clk_tree_init(void) + +{ + unsigned int reg = 0xffffffff; + + /* enable all ips clock by Clock Gating Register*/ + __raw_writel(reg, MXC_CCM_CCGR0); + __raw_writel(reg, MXC_CCM_CCGR1); + __raw_writel(reg, MXC_CCM_CCGR2); + __raw_writel(reg, MXC_CCM_CCGR3); + __raw_writel(reg, MXC_CCM_CCGR4); + __raw_writel(reg, MXC_CCM_CCGR5); + __raw_writel(reg, MXC_CCM_CCGR6); + __raw_writel(reg, MXC_CCM_CCGR7); + __raw_writel(reg, MXC_CCM_CCGR8); + __raw_writel(reg, MXC_CCM_CCGR9); + __raw_writel(reg, MXC_CCM_CCGR10); + __raw_writel(reg, MXC_CCM_CCGR11); +} + + +int __init mvf_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2) +{ + __iomem void *base; + int i; + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + apll_base = MVF_IO_ADDRESS(MVF_ANATOP_BASE_ADDR); + + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + + clk_tree_init(); + + /* Disable un-necessary PFDs & PLLs */ + + /* keep correct count. */ + cpu_clk.usecount++; + pll1_sys_main_clk.usecount += 5; + pll2_528_bus_main_clk.usecount += 5; + periph_clk.usecount++; + ipg_clk.usecount++; +#if 0 + clk_set_parent(&periph_clk, &pll2_pfd2_396M); + clk_enable(&periph_clk); /* platform bus clk */ + clk_enable(&ipg_clk); /* ips bus clk */ +#endif + clk_enable(&pll3_usb_otg_main_clk); + + base = MVF_IO_ADDRESS(MVF_PIT_BASE_ADDR); + + pit_timer_init(&pit_clk, base, MVF_INT_PIT); + + /*clk_set_parent(&enet_clk, &pll5_enet_main_clk);*/ + + clk_set_parent(&esdhc1_clk, &pll1_pfd3_396M); + clk_set_rate(&esdhc1_clk, 100000000); + + clk_set_parent(&dcu0_clk, &pll1_pfd2_452M); + clk_set_rate(&dcu0_clk, 113000000); + + clk_set_parent(&sai2_clk, &audio_external_clk); + clk_set_rate(&sai2_clk, 24576000); + + return 0; + +} diff --git a/arch/arm/mach-mvf/cpu.c b/arch/arm/mach-mvf/cpu.c new file mode 100644 index 000000000000..2254ac5974c5 --- /dev/null +++ b/arch/arm/mach-mvf/cpu.c @@ -0,0 +1,92 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/iram_alloc.h> +#include <linux/delay.h> + +#include <mach/hardware.h> +#include <asm/io.h> +#include <asm/mach/map.h> +#include <mach/mvf.h> +#include "crm_regs.h" + + +struct cpu_op *(*get_cpu_op)(int *op); +bool enable_wait_mode; + +void __iomem *gpc_base; +void __iomem *ccm_base; + +static int cpu_silicon_rev = -1; +#define SI_REV_OFFSET 0x80 + +static int get_mvf_srev(void) +{ + void __iomem *romcp = ioremap(BOOT_ROM_BASE_ADDR, SZ_8K); + u32 rev; + + if (!romcp) { + cpu_silicon_rev = -EINVAL; + return 0; + } + + rev = __raw_readl(romcp + SI_REV_OFFSET); + rev &= 0xff; + + iounmap(romcp); + if (rev == 0x10) + return IMX_CHIP_REVISION_1_0; + else if (rev == 0x11) + return IMX_CHIP_REVISION_1_1; + else if (rev == 0x20) + return IMX_CHIP_REVISION_2_0; + return 0; +} + +/* + * Returns: + * the silicon revision of the cpu + * -EINVAL - not a mvf + */ +int mvf_revision(void) +{ + + if (cpu_silicon_rev == -1) + cpu_silicon_rev = get_mvf_srev(); + + return cpu_silicon_rev; + +} +EXPORT_SYMBOL(mvf_revision); + +static int __init post_cpu_init(void) +{ + + /*iram_init(MVF_IRAM_BASE_ADDR, MVF_IRAM_SIZE);*/ + + /* Move wait routine into iRAM */ + ccm_base = MVF_IO_ADDRESS(MVF_CCM_BASE_ADDR); + + return 0; +} +postcore_initcall(post_cpu_init); diff --git a/arch/arm/mach-mvf/crm_regs.h b/arch/arm/mach-mvf/crm_regs.h new file mode 100644 index 000000000000..744dbfff2165 --- /dev/null +++ b/arch/arm/mach-mvf/crm_regs.h @@ -0,0 +1,536 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MVF_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MVF_CRM_REGS_H__ + +/* IOMUXC */ +#define MXC_IOMUXC_BASE MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR) +#define IOMUXC_GPR0 (MXC_IOMUXC_BASE + 0x00) +#define IOMUXC_GPR1 (MXC_IOMUXC_BASE + 0x04) +#define IOMUXC_GPR2 (MXC_IOMUXC_BASE + 0x08) +#define IOMUXC_GPR3 (MXC_IOMUXC_BASE + 0x0C) +#define IOMUXC_GPR4 (MXC_IOMUXC_BASE + 0x10) +#define IOMUXC_GPR5 (MXC_IOMUXC_BASE + 0x14) +#define IOMUXC_GPR6 (MXC_IOMUXC_BASE + 0x18) +#define IOMUXC_GPR7 (MXC_IOMUXC_BASE + 0x1C) +#define IOMUXC_GPR8 (MXC_IOMUXC_BASE + 0x20) +#define IOMUXC_GPR9 (MXC_IOMUXC_BASE + 0x24) +#define IOMUXC_GPR10 (MXC_IOMUXC_BASE + 0x28) +#define IOMUXC_GPR11 (MXC_IOMUXC_BASE + 0x2C) +#define IOMUXC_GPR12 (MXC_IOMUXC_BASE + 0x30) +#define IOMUXC_GPR13 (MXC_IOMUXC_BASE + 0x34) + +/* DDRMC */ +#define MXC_DDRMC_BASE MVF_IO_ADDRESS(DDRMC_BASE_ADDR) +#define DDRMC_CR00_OFFSET (MXC_DDRMC_BASE + 0x00) +/* + * dram class: b0101->lpddr2 + * b0110->ddr3 + */ +#define DDRMC_MDMISC_DDR_TYPE_MASK (0x7 << 8) +#define DDRMC_MDMISC_DDR_TYPE_OFFSET (8) + +/* PLLs */ +#define MXC_PLL_BASE MVF_IO_ADDRESS(ANADIG_BASE_ADDR) +#define PLL1_SYS_BASE_ADDR (MXC_PLL_BASE + 0x270) +#define PLL2_528_BASE_ADDR (MXC_PLL_BASE + 0x30) +#define PLL3_480_USB1_BASE_ADDR (MXC_PLL_BASE + 0x10) +#define PLL4_AUDIO_BASE_ADDR (MXC_PLL_BASE + 0x70) +#define PLL6_VIDEO_BASE_ADDR (MXC_PLL_BASE + 0xA0) +#define PLL3_480_USB2_BASE_ADDR (MXC_PLL_BASE + 0x20) +#define PLL5_ENET_BASE_ADDR (MXC_PLL_BASE + 0xE0) +#define PFD_480_BASE_ADDR (MXC_PLL_BASE + 0xF0) +#define PFD_528_BASE_ADDR (MXC_PLL_BASE + 0x100) +#define PFD_528SYS_BASE_ADDR (MXC_PLL_BASE + 0x2B0) +#define ANADIG_MISC0_REG (MXC_PLL_BASE + 0x150) +#define ANADIG_MISC1_REG (MXC_PLL_BASE + 0x160) +#define PLL_PFD_480_USB1 (MXC_PLL_BASE + 0xF0) +#define ANADIG_USB1_VBUS_DETECT (MXC_PLL_BASE + 0x1A0) +#define ANADIG_USB1_CHRG_DETECT (MXC_PLL_BASE + 0x1B0) +#define ANADIG_USB1_VBUS_DETECT_STATUS (MXC_PLL_BASE + 0x1C0) +#define ANADIG_USB1_CHRG_DETECT_STATUS (MXC_PLL_BASE + 0x1D0) +#define ANADIG_USB1_LOOPBACK (MXC_PLL_BASE + 0x1E0) +#define ANADIG_USB1_MISC (MXC_PLL_BASE + 0x1F0) +#define ANADIG_USB2_VBUS_DETECT (MXC_PLL_BASE + 0x200) +#define ANADIG_USB2_CHRG_DETECT (MXC_PLL_BASE + 0x210) +#define ANADIG_USB2_VBUS_DETECT_STATUS (MXC_PLL_BASE + 0x220) +#define ANADIG_USB2_CHRG_DETECT_STATUS (MXC_PLL_BASE + 0x230) +#define ANADIG_USB2_LOOPBACK (MXC_PLL_BASE + 0x240) +#define ANADIG_USB2_MISC (MXC_PLL_BASE + 0x250) +#define PLL_LOCK_STATUS (MXC_PLL_BASE + 0x2C0) +/* + * MXC_PLL_BASE=0x40050000 + * 32-bits registers + */ +#define USBPHY1_PWD (MXC_PLL_BASE + 0x0800 + 0x0) +#define USBPHY1_TX (MXC_PLL_BASE + 0x0800 + 0x10) +#define USBPHY1_RX (MXC_PLL_BASE + 0x0800 + 0x20) +#define USBPHY1_CTRL (MXC_PLL_BASE + 0x0800 + 0x30) +#define USBPHY1_STATUS (MXC_PLL_BASE + 0x0800 + 0x40) +#define USBPHY1_DEBUG (MXC_PLL_BASE + 0x0800 + 0x50) +#define USBPHY1_DEBUG0_STATUS (MXC_PLL_BASE + 0x0800 + 0x60) +#define USBPHY1_DEBUG1 (MXC_PLL_BASE + 0x0800 + 0x70) +#define USBPHY1_VERSION (MXC_PLL_BASE + 0x0800 + 0x80) +#define USBPHY1_IP (MXC_PLL_BASE + 0x0800 + 0x90) + +#define USBPHY2_PWD (MXC_PLL_BASE + 0x0C00 + 0x0) +#define USBPHY2_TX (MXC_PLL_BASE + 0x0C00 + 0x10) +#define USBPHY2_RX (MXC_PLL_BASE + 0x0C00 + 0x20) +#define USBPHY2_CTRL (MXC_PLL_BASE + 0x0C00 + 0x30) +#define USBPHY2_STATUS (MXC_PLL_BASE + 0x0C00 + 0x40) +#define USBPHY2_DEBUG (MXC_PLL_BASE + 0x0C00 + 0x50) +#define USBPHY2_DEBUG0_STATUS (MXC_PLL_BASE + 0x0C00 + 0x60) +#define USBPHY2_DEBUG1 (MXC_PLL_BASE + 0x0C00 + 0x70) +#define USBPHY2_VERSION (MXC_PLL_BASE + 0x0C00 + 0x80) +#define USBPHY2_IP (MXC_PLL_BASE + 0x0C00 + 0x90) + + +#define ANATOP_LVDS_CLK1_SRC_SATA 0xB +#define ANATOP_LVDS_CLK1_OBEN_MASK 0x400 +#define ANATOP_LVDS_CLK1_IBEN_MASK 0x1000 + +#define PLL_SETREG_OFFSET 0x4 +#define PLL_CLRREG_OFFSET 0x8 +#define PLL_TOGGLE_OFFSET 0x0C +#define PLL_NUM_DIV_OFFSET 0x10 +#define PLL_DENOM_DIV_OFFSET 0x20 +#define PLL_528_SS_OFFSET 0x10 +#define PLL_528_NUM_DIV_OFFSET 0x20 +#define PLL_528_DENOM_DIV_OFFSET 0x30 + +/* Common PLL register bit defines. */ +#define ANADIG_PLL_LOCK (1 << 31) +#define ANADIG_PLL_BYPASS (1 << 16) +#define ANADIG_PLL_BYPASS_CLK_SRC_MASK (0x1 << 14) +#define ANADIG_PLL_BYPASS_CLK_SRC_OFFSET (14) +#define ANADIG_PLL_ENABLE (1 << 13) +#define ANADIG_PLL_POWER_DOWN (1 << 12) +#define ANADIG_PLL_HOLD_RING_OFF (1 << 11) + +/* PLL1_SYS defines */ +#define ANADIG_PLL_SYS_DIV_SELECT_MASK (0x7F) +#define ANADIG_PLL_SYS_DIV_SELECT_OFFSET (0) + +/* PLL2_528 defines */ +#define ANADIG_PLL_528_DIV_SELECT (1) + +/* PLL3_480 defines. */ +#define ANADIG_PLL_480_EN_USB_CLKS (1 << 6) +#define ANADIG_PLL_480_DIV_SELECT_MASK (0x3) +#define ANADIG_PLL_480_DIV_SELECT_OFFSET (0) + +/* PLL4_AUDIO PLL6_VIDEO defines. */ +#define ANADIG_PLL_AV_DIV_SELECT_MASK (0x7F) +#define ANADIG_PLL_AV_DIV_SELECT_OFFSET (0) +#define ANADIG_PLL_AV_TEST_DIV_SEL_MASK (0x180000) +#define ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET (19) + +/* PLL5_ENET defines. */ +#define ANADIG_PLL_ENET_LOCK (1 << 31) +#define ANADIG_PLL_ENET_EN_SATA (1 << 20) +#define ANADIG_PLL_ENET_EN_PCIE (1 << 19) +#define ANADIG_PLL_ENET_BYPASS (1 << 16) +#define ANADIG_PLL_ENET_EN (1 << 13) +#define ANADIG_PLL_ENET_POWER_DOWN (1 << 12) +#define ANADIG_PLL_ENET_DIV_SELECT_MASK (0x3) +#define ANADIG_PLL_ENET_DIV_SELECT_OFFSET (0) + +/* PFD register defines. */ +#define ANADIG_PFD_FRAC_MASK 0x3F +#define ANADIG_PFD3_CLKGATE (1 << 31) +#define ANADIG_PFD3_STABLE (1 << 30) +#define ANADIG_PFD3_FRAC_OFFSET 24 +#define ANADIG_PFD2_CLKGATE (1 << 23) +#define ANADIG_PFD2_STABLE (1 << 22) +#define ANADIG_PFD2_FRAC_OFFSET 16 +#define ANADIG_PFD1_CLKGATE (1 << 15) +#define ANADIG_PFD1_STABLE (1 << 14) +#define ANADIG_PFD1_FRAC_OFFSET 8 +#define ANADIG_PFD0_CLKGATE (1 << 7) +#define ANADIG_PFD0_STABLE (1 << 6) +#define ANADIG_PFD0_FRAC_OFFSET 0 + +/* ANATOP Regulator/LDO defines */ +#define ANADIG_REG_RAMP_RATE_MASK 0x03 +#define ANADIG_REG_RAMP_RATE_OFFSET (0x3 << 27) +#define ANADIG_REG_ADJUST_MASK 0xF +#define ANADIG_REG_TARGET_MASK 0x1F +#define ANADIG_REG2_SOC_ADJUST_OFFSET 23 +#define ANADIG_REG2_SOC_TARGET_OFFSET 18 +#define ANADIG_REG1_PU_ADJUST_OFFSET 14 +#define ANADIG_REG1_PU_TARGET_OFFSET 9 +#define ANADIG_REG0_CORE_ADJUST_OFFSET 5 +#define ANADIG_REG0_CORE_TARGET_OFFSET 0 + +/* ANA MISC0 register defines */ +#define ANADIG_MISC0_OSC_XTALOK_EN (1 << 17) +#define ANADIG_MISC0_OSC_XTALOK (1 << 16) +#define ANADIG_MISC0_CLK_24M_IRC_XTAL_SEL (1 << 13) +#define ANADIG_MISC0_STOP_MODE_CONFIG (1 << 11) +#define ANADIG_MISC0_REFTOP_VBGUP (1 << 7) +#define ANADIG_MISC0_REFTOP_SELBIASOFF (1 << 3) +#define ANADIG_MISC0_REFTOP_LOWPOWER (1 << 2) +#define ANADIG_MISC0_REFTOP_PWDVBGUP (1 << 1) +#define ANADIG_MISC0_REFTOP_PWD (1 << 0) + + +#define MXC_CCM_BASE MVF_IO_ADDRESS(MVF_CCM_BASE_ADDR) + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x04) +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x0c) +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x14) +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x18) +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x1c) +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x2c) +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x30) +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x3c) +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x44) +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x48) +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x4c) +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x50) +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x54) +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x58) +#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x5c) +#define MXC_CCM_CCGR8 (MXC_CCM_BASE + 0x60) +#define MXC_CCM_CCGR9 (MXC_CCM_BASE + 0x64) +#define MXC_CCM_CCGR10 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_CCGR11 (MXC_CCM_BASE + 0x6C) +#define MXC_CCM_CMEOR0 (MXC_CCM_BASE + 0x70) +#define MXC_CCM_CMEOR1 (MXC_CCM_BASE + 0x74) +#define MXC_CCM_CMEOR2 (MXC_CCM_BASE + 0x78) +#define MXC_CCM_CMEOR3 (MXC_CCM_BASE + 0x7C) +#define MXC_CCM_CMEOR4 (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CMEOR5 (MXC_CCM_BASE + 0x84) +#define MXC_CCM_CPPDSR (MXC_CCM_BASE + 0x88) +#define MXC_CCM_CCOWR (MXC_CCM_BASE + 0x8C) +#define MXC_CCM_CCPGR0 (MXC_CCM_BASE + 0x90) +#define MXC_CCM_CCPGR1 (MXC_CCM_BASE + 0x94) +#define MXC_CCM_CCPGR2 (MXC_CCM_BASE + 0x98) +#define MXC_CCM_CCPGR3 (MXC_CCM_BASE + 0x9C) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_FIRC_EN (1 << 16) +#define MXC_CCM_CCR_COSC_EN (1 << 12) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSC_READY (1 << 5) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_PLL3_PFD4_EN (1 << 31) +#define MXC_CCM_CCSR_PLL3_PFD3_EN (1 << 30) +#define MXC_CCM_CCSR_PLL3_PFD2_EN (1 << 29) +#define MXC_CCM_CCSR_PLL3_PFD1_EN (1 << 28) +#define MXC_CCM_CCSR_DAP_EN (1 << 24) +#define MXC_CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET (19) +#define MXC_CCM_CCSR_PLL2_PFD_CLK_SLE_MASK (0x7 << 19) +#define MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET (16) +#define MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) +#define MXC_CCM_CCSR_PLL2_PFD4_EN (1 << 15) +#define MXC_CCM_CCSR_PLL2_PFD3_EN (1 << 14) +#define MXC_CCM_CCSR_PLL2_PFD2_EN (1 << 13) +#define MXC_CCM_CCSR_PLL2_PFD1_EN (1 << 12) +#define MXC_CCM_CCSR_PLL1_PFD4_EN (1 << 11) +#define MXC_CCM_CCSR_PLL1_PFD3_EN (1 << 10) +#define MXC_CCM_CCSR_PLL1_PFD2_EN (1 << 9) +#define MXC_CCM_CCSR_PLL1_PFD1_EN (1 << 8) +#define MXC_CCM_CCSR_DDRC_CLK_SEL_OFFSET (6) +#define MXC_CCM_CCSR_DDRC_CLK_SEL_MASK (1 << 6) +#define MXC_CCM_CCSR_FAST_CLK_SEL_OFFSET (5) +#define MXC_CCM_CCSR_FAST_CLK_SEL_MASK (1 << 5) +#define MXC_CCM_CCSR_SLOW_CLK_SEL_OFFSET (4) +#define MXC_CCM_CCSR_SLOW_CLK_SEL_MASK (1 << 4) +#define MXC_CCM_CCSR_CA5_CLK_SEL_OFFSET (3) +#define MXC_CCM_CCSR_CA5_CLK_SEL_MASK (1 << 3) +#define MXC_CCM_CCSR_SYS_CLK_SEL_OFFSET (0) +#define MXC_CCM_CCSR_SYS_CLK_SEL_MASK (0x7) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_FLEX_CLK_DIV_OFFSET (22) +#define MXC_CCM_CACRR_FLEX_CLK_DIV_MASK (0x7 << 22) +#define MXC_CCM_CACRR_PLL6_CLK_DIV_OFFSET (21) +#define MXC_CCM_CACRR_PLL3_CLK_DIV_OFFSET (20) +#define MXC_CCM_CACRR_PLL1_CLK_DIV_OFFSET (16) +#define MXC_CCM_CACRR_PLL1_CLK_DIV_MASK (0x3 << 16) +#define MXC_CCM_CACRR_IPG_CLK_DIV_OFFSET (11) +#define MXC_CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) +#define MXC_CCM_CACRR_PLL4_CLK_DIV_OFFSET (6) +#define MXC_CCM_CACRR_PLL4_CLK_DIV_MASK (0x7 << 6) +#define MXC_CCM_CACRR_BUS_CLK_DIV_OFFSET (3) +#define MXC_CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) +#define MXC_CCM_CACRR_ARM_CLK_DIV_OFFSET (0) +#define MXC_CCM_CACRR_ARM_CLK_DIV_MASK (0x7) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_DCU1_CLK_SEL_OFFSET (29) +#define MXC_CCM_CSCMR1_DCU1_CLK_SEL_MASK (1 << 29) +#define MXC_CCM_CSCMR1_DCU0_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_DCU0_CLK_SEL_MASK (1 << 28) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_ESAI_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESAI_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (18) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CSCMR1_ESDHC0_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC0_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_GCC_CLK_SEL_OFFSET (1 << 14) +#define MXC_CCM_CSCMR1_NFC_CLK_SEL_OFFSET (1 << 12) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (1 << 10) +#define MXC_CCM_CSCMR1_VADC_CLK_SEL_OFFSET (1 << 8) +#define MXC_CCM_CSCMR1_SAI3_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CSCMR1_SAI2_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SAI1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SAI0_CLK_SEL_OFFSET (0) +#define MXC_CCM_CSCMR1_SAI0_CLK_SEL_MASK (0x3) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_FTM3_CLK_EN (0x1 << 28) +#define MXC_CCM_CSCDR1_FTM2_CLK_EN (0x1 << 27) +#define MXC_CCM_CSCDR1_FTM1_CLK_EN (0x1 << 26) +#define MXC_CCM_CSCDR1_FTM0_CLK_EN (0x1 << 25) +#define MXC_CCM_CSCDR1_RMII_CLK_EN (0x1 << 24) +#define MXC_CCM_CSCDR1_ENET_TS_EN (0x1 << 23) +#define MXC_CCM_CSCDR1_VADC_EN (0x1 << 22) +#define MXC_CCM_CSCDR1_VADC_DIV_OFFSET 20 +#define MXC_CCM_CSCDR1_VADC_DIV_MASK (0x3 << 20) +#define MXC_CCM_CSCDR1_SAI3_EN (0x1 << 19) +#define MXC_CCM_CSCDR1_SAI2_EN (0x1 << 18) +#define MXC_CCM_CSCDR1_SAI1_EN (0x1 << 17) +#define MXC_CCM_CSCDR1_SAI0_EN (0x1 << 16) +#define MXC_CCM_CSCDR1_SAI3_DIV_OFFSET (12) +#define MXC_CCM_CSCDR1_SAI3_DIV_MASK (0xF << 12) +#define MXC_CCM_CSCDR1_SAI2_DIV_OFFSET (8) +#define MXC_CCM_CSCDR1_SAI2_DIV_MASK (0xF << 8) +#define MXC_CCM_CSCDR1_SAI1_DIV_OFFSET (4) +#define MXC_CCM_CSCDR1_SAI1_DIV_MASK (0xF << 4) +#define MXC_CCM_CSCDR1_SAI0_DIV_OFFSET (0) +#define MXC_CCM_CSCDR1_SAI0_DIV_MASK (0xF << 0) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_ESAI_EN (0x1 << 30) +#define MXC_CCM_CSCDR2_ESDHC1_EN (0x1 << 29) +#define MXC_CCM_CSCDR2_ESDHC0_EN (0x1 << 28) +#define MXC_CCM_CSCDR2_ESAI_DIV_MASK (0xF << 24) +#define MXC_CCM_CSCDR2_ESAI_DIV_OFFSET (24) +#define MXC_CCM_CSCDR2_ESDHC1_DIV_MASK (0xF << 20) +#define MXC_CCM_CSCDR2_ESDHC1_DIV_OFFSET (20) +#define MXC_CCM_CSCDR2_ESDHC0_DIV_MASK (0xF << 16) +#define MXC_CCM_CSCDR2_ESDHC0_DIV_OFFSET (16) +#define MXC_CCM_CSCDR2_NFC_CLK_INV (0x1 << 14) +#define MXC_CCM_CSCDR2_NFC_FRAC_DIV_EN (0x1 << 13) +#define MXC_CCM_CSCDR2_CAN1_EN (0x1 << 12) +#define MXC_CCM_CSCDR2_CAN0_EN (0x1 << 11) +#define MXC_CCM_CSCDR2_GPU_EN (0x1 << 10) +#define MXC_CCM_CSCDR2_NFC_EN (0x1 << 9) +#define MXC_CCM_CSCDR2_SPDIF_EN (0x1 << 8) +#define MXC_CCM_CSCDR2_NFC_FRAC_OFFSET (4) +#define MXC_CCM_CSCDR2_NFC_DIV_MASK (0xF << 4) +#define MXC_CCM_CSCDR2_SPDIF_DIV_OFFSET (0) +#define MXC_CCM_CSCDR2_SPDIF_DIV_MASK (0xF) + +/* Define the bits in register CSCDR3 */ +#define MXC_CCM_CSCDR3_SWO_EN (0x1 << 28) +#define MXC_CCM_CSCDR3_SWO_DIV (0x1 << 27) +#define MXC_CCM_CSCDR3_TRACE_EN (0x1 << 26) +#define MXC_CCM_CSCDR3_TRACE_DIV_MASK (0x3 << 24) +#define MXC_CCM_CSCDR3_TRACE_DIV_OFFSET (24) +#define MXC_CCM_CSCDR3_DCU1_EN (0x1 << 23) +#define MXC_CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20) +#define MXC_CCM_CSCDR3_DCU1_DIV_OFFSET (20) +#define MXC_CCM_CSCDR3_DCU0_EN (0x1 << 19) +#define MXC_CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_DCU0_DIV_OFFSET (16) +#define MXC_CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) +#define MXC_CCM_CSCDR3_NFC_PRE_DIV_OFFSET (13) +#define MXC_CCM_CSCDR3_QSPI1_EN (0x1 << 12) +#define MXC_CCM_CSCDR3_QSPI1_DIV (0x1 << 11) +#define MXC_CCM_CSCDR3_QSPI1_X2_DIV (0x1 << 10) +#define MXC_CCM_CSCDR3_QSPI1_X4_DIV_MASK (0x3 << 8) +#define MXC_CCM_CSCDR3_QSPI1_X4_DIV_OFFSET (8) +#define MXC_CCM_CSCDR3_QSPI0_EN (0x1 << 4) +#define MXC_CCM_CSCDR3_QSPI0_DIV (0x1 << 3) +#define MXC_CCM_CSCDR3_QSPI0_X2_DIV (0x1 << 2) +#define MXC_CCM_CSCDR3_QSPI0_X4_DIV_OFFSET (0) +#define MXC_CCM_CSCDR3_QSPI0_X4_DIV_MASK (0x3) + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_SWO_CLK_SEL (1 << 19) +#define MXC_CCM_CSCMR2_TRACE_CLK_SEL (1 << 18) +#define MXC_CCM_CSCMR2_FTM3_FIX_CLK_SEL (1 << 17) +#define MXC_CCM_CSCMR2_FTM2_FIX_CLK_SEL (1 << 16) +#define MXC_CCM_CSCMR2_FTM1_FIX_CLK_SEL (1 << 15) +#define MXC_CCM_CSCMR2_FTM0_FIX_CLK_SEL (1 << 14) +#define MXC_CCM_CSCMR2_FTM3_EXT_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR2_FTM3_EXT_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR2_FTM2_EXT_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR2_FTM2_EXT_CLK_SEL_OFFSET (10) +#define MXC_CCM_CSCMR2_FTM1_EXT_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR2_FTM1_EXT_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR2_FTM0_EXT_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CSCMR2_FTM0_EXT_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR2_RMII_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_MASK (0x7) +#define MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_OFFSET (0) + +/* Define the bits in register CSCDR4 */ +#define MXC_CCM_CSCDR4_SNVS_CLK_DIV_MASK (0x7F) +#define MXC_CCM_CSCDR4_SNVS_CLK_DIV_OFFSET (0) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_M_L2CC_IDLE (1 << 25) +#define MXC_CCM_CLPCR_M_SCU_IDLE (1 << 24) +#define MXC_CCM_CLPCR_M_CORE1_WFI (1 << 23) +#define MXC_CCM_CLPCR_M_CORE0_WFI (1 << 22) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) +#define MXC_CCM_CLPCR_ANATOP_STOP_MODE (1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) +#define MXC_CCM_CLPCR_SBYOS (1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_LPM (1 << 5) + +/* CISR */ +#define MXC_CCM_CISR_COSC_READY (1 << 6) +#define MXC_CCM_CISR_LRF_PLL4 (1 << 3) +#define MXC_CCM_CISR_LRF_PLL3 (1 << 2) +#define MXC_CCM_CISIR_LRF_PLL2 (1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (1) + +/* CIMR */ +#define MXC_CCM_CIMR_COSC_READY (1 << 6) +#define MXC_CCM_CIMR_LRF_PLL4 (1 << 3) +#define MXC_CCM_CIMR_LRF_PLL3 (1 << 2) +#define MXC_CCM_CIMR_LRF_PLL2 (1 << 1) +#define MXC_CCM_CIMR_LRF_PLL1 (1) + +/* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG (1 << 4) +#define MXC_CCM_CGPR_QSPI1_ACCZ (1 << 1) +#define MXC_CCM_CGPR_QSPI0_ACCZ (1) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGRx_CG_MASK 0x3 +#define MXC_CCM_CCGRx_MOD_OFF 0x0 +#define MXC_CCM_CCGRx_MOD_ALWAYS_ON 0x2 +#define MXC_CCM_CCGRx_MOD_ON 0x3 +#define MXC_CCM_CCGRx_MOD_IDLE 0x1 + +#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) +#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGRx_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) +#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) + +#define MXC_CCM_CCGRx_CG114_OFFSET 30 + +#define MXC_CCM_CCGRx_CG15_OFFSET 30 +#define MXC_CCM_CCGRx_CG14_OFFSET 28 +#define MXC_CCM_CCGRx_CG13_OFFSET 26 +#define MXC_CCM_CCGRx_CG12_OFFSET 24 +#define MXC_CCM_CCGRx_CG11_OFFSET 22 +#define MXC_CCM_CCGRx_CG10_OFFSET 20 +#define MXC_CCM_CCGRx_CG9_OFFSET 18 +#define MXC_CCM_CCGRx_CG8_OFFSET 16 +#define MXC_CCM_CCGRx_CG7_OFFSET 14 +#define MXC_CCM_CCGRx_CG6_OFFSET 12 +#define MXC_CCM_CCGRx_CG5_OFFSET 10 +#define MXC_CCM_CCGRx_CG4_OFFSET 8 +#define MXC_CCM_CCGRx_CG3_OFFSET 6 +#define MXC_CCM_CCGRx_CG2_OFFSET 4 +#define MXC_CCM_CCGRx_CG1_OFFSET 2 +#define MXC_CCM_CCGRx_CG0_OFFSET 0 + +/* CMEOR */ + +/* CPPDSR */ +#define MXC_CCM_CPPDSR_PLL3_PFD4_STAT (0x1 << 11) +#define MXC_CCM_CPPDSR_PLL3_PFD3_STAT (0x1 << 10) +#define MXC_CCM_CPPDSR_PLL3_PFD2_STAT (0x1 << 9) +#define MXC_CCM_CPPDSR_PLL3_PFD1_STAT (0x1 << 8) +#define MXC_CCM_CPPDSR_PLL2_PFD4_STAT (0x1 << 7) +#define MXC_CCM_CPPDSR_PLL2_PFD3_STAT (0x1 << 6) +#define MXC_CCM_CPPDSR_PLL2_PFD2_STAT (0x1 << 5) +#define MXC_CCM_CPPDSR_PLL2_PFD1_STAT (0x1 << 4) +#define MXC_CCM_CPPDSR_PLL1_PFD4_STAT (0x1 << 3) +#define MXC_CCM_CPPDSR_PLL1_PFD3_STAT (0x1 << 2) +#define MXC_CCM_CPPDSR_PLL1_PFD2_STAT (0x1 << 1) +#define MXC_CCM_CPPDSR_PLL1_PFD1_STAT (0x1) + + +/* CCOWR */ +#define MXC_CCM_CCOWR_AUX_CORE_WKUP (0x1 << 16) + +/* CCPGR */ +#define MXC_CCM_CCPGRx_PPCG_MASK 0x3 +#define MXC_CCM_CCPGRx_MOD_OFF 0x0 +#define MXC_CCM_CCPGRx_MOD_ALWAYS_ON 0x2 +#define MXC_CCM_CCPGRx_MOD_ON 0x3 +#define MXC_CCM_CCPGRx_MOD_IDLE 0x1 + +#define MXC_CCM_CCPGRx_PPCG15_MASK (0x3 << 30) +#define MXC_CCM_CCPGRx_PPCG14_MASK (0x3 << 28) +#define MXC_CCM_CCPGRx_PPCG13_MASK (0x3 << 26) +#define MXC_CCM_CCPGRx_PPCG12_MASK (0x3 << 24) +#define MXC_CCM_CCPGRx_PPCG11_MASK (0x3 << 22) +#define MXC_CCM_CCPGRx_PPCG10_MASK (0x3 << 20) +#define MXC_CCM_CCPGRx_PPCG9_MASK (0x3 << 18) +#define MXC_CCM_CCPGRx_PPCG8_MASK (0x3 << 16) +#define MXC_CCM_CCPGRx_PPCG7_MASK (0x3 << 14) +#define MXC_CCM_CCPGRx_PPCG5_MASK (0x3 << 10) +#define MXC_CCM_CCPGRx_PPCG4_MASK (0x3 << 8) +#define MXC_CCM_CCPGRx_PPCG3_MASK (0x3 << 6) +#define MXC_CCM_CCPGRx_PPCG2_MASK (0x3 << 4) +#define MXC_CCM_CCPGRx_PPCG1_MASK (0x3 << 2) +#define MXC_CCM_CCPGRx_PPCG0_MASK (0x3 << 0) + +#define MXC_CCM_CCPGRx_PPCG15_OFFSET 30 +#define MXC_CCM_CCPGRx_PPCG14_OFFSET 28 +#define MXC_CCM_CCPGRx_PPCG13_OFFSET 26 +#define MXC_CCM_CCPGRx_PPCG12_OFFSET 24 +#define MXC_CCM_CCPGRx_PPCG11_OFFSET 22 +#define MXC_CCM_CCPGRx_PPCG10_OFFSET 20 +#define MXC_CCM_CCPGRx_PPCG9_OFFSET 18 +#define MXC_CCM_CCPGRx_PPCG8_OFFSET 16 +#define MXC_CCM_CCPGRx_PPCG7_OFFSET 14 +#define MXC_CCM_CCPGRx_PPCG6_OFFSET 12 +#define MXC_CCM_CCPGRx_PPCG5_OFFSET 10 +#define MXC_CCM_CCPGRx_CG4_OFFSET 8 +#define MXC_CCM_CCPGRx_PCG3_OFFSET 6 +#define MXC_CCM_CCPGRx_PPCG2_OFFSET 4 +#define MXC_CCM_CCPGRx_PPCG1_OFFSET 2 +#define MXC_CCM_CCPGRx_PPCG0_OFFSET 0 + +#endif /* __ARCH_ARM_MACH_MVF_CRM_REGS_H__ */ diff --git a/arch/arm/mach-mvf/devices-mvf.h b/arch/arm/mach-mvf/devices-mvf.h new file mode 100644 index 000000000000..e96c7edd0395 --- /dev/null +++ b/arch/arm/mach-mvf/devices-mvf.h @@ -0,0 +1,209 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/mvf.h> +#include <mach/devices-common.h> + +extern const struct imx_imx_uart_1irq_data mvf_imx_uart_data[] __initconst; +#define mvf_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&mvf_imx_uart_data[id], pdata) + +extern const struct imx_snvs_rtc_data mvf_snvs_rtc_data __initconst; +#define mvf_add_snvs_rtc() \ + imx_add_snvs_rtc(&mvf_snvs_rtc_data) + +extern const struct imx_fec_data mvf_fec_data __initconst; +#define mvf_add_fec(pdata) \ + imx_add_fec(&mvf_fec_data, pdata) + +extern const struct imx_sdhci_esdhc_imx_data +mvf_sdhci_esdhc_imx_data[] __initconst; +#define mvf_add_sdhci_esdhc_imx(id, pdata) \ + imx_add_sdhci_esdhc_imx(&mvf_sdhci_esdhc_imx_data[id], pdata) + +extern const struct imx_spi_imx_data mvf_dspi_data[] __initconst; +#define mvf_add_dspi(id, pdata) \ + mvf_add_spi_mvf(&mvf_dspi_data[id], pdata) + +extern const struct imx_imx_i2c_data mvf_i2c_data[] __initconst; +#define mvf_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&mvf_i2c_data[id], pdata) + +extern const struct imx_mxc_nand_data mvf_nand_data __initconst; +#define mvf_add_nand(pdata) \ + imx_add_mxc_nand(&mvf_nand_data, pdata) + +extern const struct imx_fsl_usb2_udc_data mvf_fsl_usb2_udc_data __initconst; +#define mvf_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&mvf_fsl_usb2_udc_data, pdata) + +extern const struct imx_mxc_ehci_data mvf_mxc_ehci_otg_data __initconst; +#define mvf_add_fsl_ehci_otg(pdata) \ + imx_add_fsl_ehci(&mvf_mxc_ehci_otg_data, pdata) + +extern const struct imx_mxc_ehci_data mvf_mxc_ehci_hs_data[] __initconst; +#define mvf_add_fsl_ehci_hs(id, pdata) \ + imx_add_fsl_ehci(&mvf_mxc_ehci_hs_data[id - 1], pdata) + +extern const struct imx_fsl_usb2_otg_data mvf_fsl_usb2_otg_data __initconst; +#define mvf_add_fsl_usb2_otg(pdata) \ + imx_add_fsl_usb2_otg(&mvf_fsl_usb2_otg_data, pdata) + +extern +const struct imx_fsl_usb2_wakeup_data mvf_fsl_otg_wakeup_data __initconst; +#define mvf_add_fsl_usb2_otg_wakeup(pdata) \ + imx_add_fsl_usb2_wakeup(&mvf_fsl_otg_wakeup_data, pdata) + +extern +const struct imx_fsl_usb2_wakeup_data mvf_fsl_hs_wakeup_data[] __initconst; +#define mvf_add_fsl_usb2_hs_wakeup(id, pdata) \ + imx_add_fsl_usb2_wakeup(&mvf_fsl_hs_wakeup_data[id - 1], pdata) + +extern const struct imx_imx_esai_data mvf_imx_esai_data[] __initconst; +#define mvf_add_imx_esai(id, pdata) \ + imx_add_imx_esai(&mvf_imx_esai_data[id], pdata) + +extern const struct imx_viv_gpu_data mvf_gpu_data __initconst; + +extern const struct imx_ahci_data mvf_ahci_data __initconst; +#define mvf_add_ahci(id, pdata) \ + imx_add_ahci(&mvf_ahci_data, pdata) + +extern const struct imx_imx_ssi_data mvf_imx_ssi_data[] __initconst; +#define mvf_add_imx_ssi(id, pdata) \ + imx_add_imx_ssi(&mvf_imx_ssi_data[id], pdata) + +extern const struct imx_ipuv3_data mvf_ipuv3_data[] __initconst; +#define mvf_add_ipuv3(id, pdata) imx_add_ipuv3(id, &mvf_ipuv3_data[id], pdata) +#define mvf_add_ipuv3fb(id, pdata) imx_add_ipuv3_fb(id, pdata) + +#define mvf_add_lcdif(pdata) \ + platform_device_register_resndata(NULL, "mxc_lcdif",\ + 0, NULL, 0, pdata, sizeof(*pdata)); + +extern const struct imx_ldb_data mvf_ldb_data __initconst; +#define mvf_add_ldb(pdata) \ + imx_add_ldb(&mvf_ldb_data, pdata); + +#define mvf_add_v4l2_output(id) \ + platform_device_register_resndata(NULL, "mxc_v4l2_output",\ + id, NULL, 0, NULL, 0); + +#define mvf_add_v4l2_capture(id) \ + platform_device_register_resndata(NULL, "mxc_v4l2_capture",\ + id, NULL, 0, NULL, 0); + +extern const struct imx_mxc_hdmi_data mvf_mxc_hdmi_data __initconst; +#define mvf_add_mxc_hdmi(pdata) \ + imx_add_mxc_hdmi(&mvf_mxc_hdmi_data, pdata) + +extern const struct imx_mxc_hdmi_core_data mvf_mxc_hdmi_core_data __initconst; +#define mvf_add_mxc_hdmi_core(pdata) \ + imx_add_mxc_hdmi_core(&mvf_mxc_hdmi_core_data, pdata) + +extern const struct imx_vpu_data mvf_vpu_data __initconst; +#define mvf_add_vpu() imx_add_vpu(&mvf_vpu_data) + +extern const struct mvf_dcu_data mvfa5_dcu_data[] __initconst; +#define mvfa5_add_dcu(id, pdata) mvf_add_dcu(id, &mvfa5_dcu_data[id], pdata) + +extern const struct mvf_sai_data mvfa5_sai_data[] __initconst; +#define mvfa5_add_sai(id, pdata) \ + mvf_add_sai(id, &mvfa5_sai_data[id], pdata) + +extern const struct imx_otp_data mvf_otp_data __initconst; +#define mvf_add_otp() \ + imx_add_otp(&mvf_otp_data) + +extern const struct imx_viim_data mvf_viim_data __initconst; +#define mvf_add_viim() \ + imx_add_viim(&mvf_viim_data) + +extern const struct imx_imx2_wdt_data mvf_imx2_wdt_data[] __initconst; +#define mvf_add_imx2_wdt(id, pdata) \ + imx_add_imx2_wdt(&mvf_imx2_wdt_data[id]) + +extern const struct imx_pm_imx_data mvf_pm_imx_data __initconst; +#define mvf_add_pm_imx(id, pdata) \ + imx_add_pm_imx(&mvf_pm_imx_data, pdata) + +extern const struct imx_imx_asrc_data mvf_imx_asrc_data[] __initconst; +#define mvf_add_asrc(pdata) \ + imx_add_imx_asrc(mvf_imx_asrc_data, pdata) + +extern const struct imx_dvfs_core_data mvf_dvfs_core_data __initconst; +#define mvf_add_dvfs_core(pdata) \ + imx_add_dvfs_core(&mvf_dvfs_core_data, pdata) + +extern const struct imx_viv_gpu_data mvf_gc2000_data __initconst; +extern const struct imx_viv_gpu_data mvf_gc320_data __initconst; +extern const struct imx_viv_gpu_data mvf_gc355_data __initconst; + +extern const struct imx_mxc_pwm_data mvf_mxc_pwm_data[] __initconst; +#define mvf_add_mxc_pwm(id) \ + imx_add_mxc_pwm(&mvf_mxc_pwm_data[id]) + +#define mvf_add_mxc_pwm_backlight(id, pdata) \ + platform_device_register_resndata(NULL, "pwm-backlight",\ + id, NULL, 0, pdata, sizeof(*pdata)); + +extern const struct imx_spdif_data mvf_imx_spdif_data __initconst; +#define mvf_add_spdif(pdata) imx_add_spdif(&mvf_imx_spdif_data, pdata) + +extern const struct imx_spdif_dai_data mvf_spdif_dai_data __initconst; +#define mvf_add_spdif_dai() imx_add_spdif_dai(&mvf_spdif_dai_data) + +#define mvf_add_spdif_audio_device(pdata) imx_add_spdif_audio_device() + +#define mvf_add_hdmi_soc() imx_add_hdmi_soc() +extern const struct imx_hdmi_soc_data mvf_imx_hdmi_soc_dai_data __initconst; +#define mvf_add_hdmi_soc_dai() \ + imx_add_hdmi_soc_dai(&mvf_imx_hdmi_soc_dai_data) + +extern const struct imx_mipi_dsi_data mvf_mipi_dsi_data __initconst; +#define mvf_add_mipi_dsi(pdata) \ + imx_add_mipi_dsi(&mvf_mipi_dsi_data, pdata) + +extern const struct imx_flexcan_data mvf_flexcan_data[] __initconst; +#define mvf_add_flexcan(id, pdata) \ + imx_add_flexcan(&mvf_flexcan_data[id], pdata) +#define mvf_add_flexcan0(pdata) mvf_add_flexcan(0, pdata) +#define mvf_add_flexcan1(pdata) mvf_add_flexcan(1, pdata) + +extern const struct imx_mipi_csi2_data mvf_mipi_csi2_data __initconst; +#define mvf_add_mipi_csi2(pdata) \ + imx_add_mipi_csi2(&mvf_mipi_csi2_data, pdata) + +extern const struct imx_perfmon_data mvf_perfmon_data[] __initconst; +#define mvf_add_perfmon(id) \ + imx_add_perfmon(&mvf_perfmon_data[id]) + +extern const struct imx_mxc_mlb_data mvf_mxc_mlb150_data __initconst; +#define mvf_add_mlb150(pdata) \ + imx_add_mlb(pdata) + +extern const struct imx_pxp_data mvf_pxp_data __initconst; +#define mvf_add_imx_pxp() \ + imx_add_imx_pxp(&mvf_pxp_data) + +#define mvf_add_imx_pxp_client() \ + imx_add_imx_pxp_client() + +extern const struct imx_epdc_data mvf_epdc_data __initconst; +#define mvf_add_imx_epdc(pdata) \ + imx_add_imx_epdc(&mvf_epdc_data, pdata) diff --git a/arch/arm/mach-mvf/devices.c b/arch/arm/mach-mvf/devices.c new file mode 100644 index 000000000000..6db1ab4f9713 --- /dev/null +++ b/arch/arm/mach-mvf/devices.c @@ -0,0 +1,78 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/ipu.h> +#include <linux/fb.h> +#include <linux/delay.h> +#include <linux/uio_driver.h> +#include <linux/iram_alloc.h> +#include <linux/fsl_devices.h> +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/gpio.h> +#include <mach/mvf.h> + +static struct mxc_gpio_port mvf_gpio_ports[] = { + { + .chip.label = "gpio-0", + .base = MVF_IO_ADDRESS(MVF_GPIO1_BASE_ADDR), + .base_int = MVF_IO_ADDRESS(MVF_GPIO1_INT_BASE_ADDR), + .irq = MVF_INT_GPIO0, + .virtual_irq_start = MXC_GPIO_IRQ_START + }, + { + .chip.label = "gpio-1", + .base = MVF_IO_ADDRESS(MVF_GPIO2_BASE_ADDR), + .base_int = MVF_IO_ADDRESS(MVF_GPIO2_INT_BASE_ADDR), + .irq = MVF_INT_GPIO1, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 + }, + { + .chip.label = "gpio-2", + .base = MVF_IO_ADDRESS(MVF_GPIO3_BASE_ADDR), + .base_int = MVF_IO_ADDRESS(MVF_GPIO3_INT_BASE_ADDR), + .irq = MVF_INT_GPIO2, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 + }, + { + .chip.label = "gpio-3", + .base = MVF_IO_ADDRESS(MVF_GPIO4_BASE_ADDR), + .base_int = MVF_IO_ADDRESS(MVF_GPIO4_INT_BASE_ADDR), + .irq = MVF_INT_GPIO3, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 + }, + { + .chip.label = "gpio-4", + .base = MVF_IO_ADDRESS(MVF_GPIO5_BASE_ADDR), + .base_int = MVF_IO_ADDRESS(MVF_GPIO5_INT_BASE_ADDR), + .irq = MVF_INT_GPIO4, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4 + }, +}; + +int mvf_register_gpios(void) +{ + /* 5 ports for MVF */ + return mxc_gpio_init(mvf_gpio_ports, 5); +} diff --git a/arch/arm/mach-mvf/dummy_gpio.c b/arch/arm/mach-mvf/dummy_gpio.c new file mode 100644 index 000000000000..3fea356cec36 --- /dev/null +++ b/arch/arm/mach-mvf/dummy_gpio.c @@ -0,0 +1,124 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/errno.h> +#include <linux/module.h> + +void gpio_uart_active(int port, int no_irda) {} +EXPORT_SYMBOL(gpio_uart_active); + +void gpio_uart_inactive(int port, int no_irda) {} +EXPORT_SYMBOL(gpio_uart_inactive); + +void gpio_gps_active(void) {} +EXPORT_SYMBOL(gpio_gps_active); + +void gpio_gps_inactive(void) {} +EXPORT_SYMBOL(gpio_gps_inactive); + +void config_uartdma_event(int port) {} +EXPORT_SYMBOL(config_uartdma_event); + +void gpio_spi_active(int cspi_mod) {} +EXPORT_SYMBOL(gpio_spi_active); + +void gpio_spi_inactive(int cspi_mod) {} +EXPORT_SYMBOL(gpio_spi_inactive); + +void gpio_owire_active(void) {} +EXPORT_SYMBOL(gpio_owire_active); + +void gpio_owire_inactive(void) {} +EXPORT_SYMBOL(gpio_owire_inactive); + +void gpio_i2c_active(int i2c_num) {} +EXPORT_SYMBOL(gpio_i2c_active); + +void gpio_i2c_inactive(int i2c_num) {} +EXPORT_SYMBOL(gpio_i2c_inactive); + +void gpio_i2c_hs_active(void) {} +EXPORT_SYMBOL(gpio_i2c_hs_active); + +void gpio_i2c_hs_inactive(void) {} +EXPORT_SYMBOL(gpio_i2c_hs_inactive); + +void gpio_pmic_active(void) {} +EXPORT_SYMBOL(gpio_pmic_active); + +void gpio_activate_audio_ports(void) {} +EXPORT_SYMBOL(gpio_activate_audio_ports); + +void gpio_sdhc_active(int module) {} +EXPORT_SYMBOL(gpio_sdhc_active); + +void gpio_sdhc_inactive(int module) {} +EXPORT_SYMBOL(gpio_sdhc_inactive); + +void gpio_sensor_select(int sensor) {} + +void gpio_sensor_active(unsigned int csi) {} +EXPORT_SYMBOL(gpio_sensor_active); + +void gpio_sensor_inactive(unsigned int csi) {} +EXPORT_SYMBOL(gpio_sensor_inactive); + +void gpio_ata_active(void) {} +EXPORT_SYMBOL(gpio_ata_active); + +void gpio_ata_inactive(void) {} +EXPORT_SYMBOL(gpio_ata_inactive); + +void gpio_nand_active(void) {} +EXPORT_SYMBOL(gpio_nand_active); + +void gpio_nand_inactive(void) {} +EXPORT_SYMBOL(gpio_nand_inactive); + +void gpio_keypad_active(void) {} +EXPORT_SYMBOL(gpio_keypad_active); + +void gpio_keypad_inactive(void) {} +EXPORT_SYMBOL(gpio_keypad_inactive); + +int gpio_usbotg_hs_active(void) +{ + return 0; +} +EXPORT_SYMBOL(gpio_usbotg_hs_active); + +void gpio_usbotg_hs_inactive(void) {} +EXPORT_SYMBOL(gpio_usbotg_hs_inactive); + +void gpio_fec_active(void) {} +EXPORT_SYMBOL(gpio_fec_active); + +void gpio_fec_inactive(void) {} +EXPORT_SYMBOL(gpio_fec_inactive); + +void gpio_spdif_active(void) {} +EXPORT_SYMBOL(gpio_spdif_active); + +void gpio_spdif_inactive(void) {} +EXPORT_SYMBOL(gpio_spdif_inactive); + +void gpio_mlb_active(void) {} +EXPORT_SYMBOL(gpio_mlb_active); + +void gpio_mlb_inactive(void) {} +EXPORT_SYMBOL(gpio_mlb_inactive); diff --git a/arch/arm/mach-mvf/irq.c b/arch/arm/mach-mvf/irq.c new file mode 100644 index 000000000000..c3e7b9291faa --- /dev/null +++ b/arch/arm/mach-mvf/irq.c @@ -0,0 +1,67 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <asm/hardware/gic.h> +#include <mach/hardware.h> + +int mvf_register_gpios(void); +unsigned int gpc_wake_irq[4]; + +static int mvf_gic_irq_set_wake(struct irq_data *d, unsigned int enable) +{ + if ((d->irq < MXC_INT_START) || (d->irq > MXC_INT_END)) { + printk(KERN_ERR "Invalid irq number!\n"); + return -EINVAL; + } + + if (enable) { + gpc_wake_irq[d->irq / 32 - 1] |= 1 << (d->irq % 32); + printk(KERN_INFO "add wake up source irq %d\n", d->irq); + } else { + printk(KERN_INFO "remove wake up source irq %d\n", d->irq); + gpc_wake_irq[d->irq / 32 - 1] &= ~(1 << (d->irq % 32)); + } + return 0; +} +void mvf_init_irq(void) +{ + unsigned int i; + void __iomem *int_router_base = + MVF_IO_ADDRESS(MVF_MSCM_INT_ROUTER_BASE); + + /* start offset if private timer irq id, which is 29. + * ID table: + * Global timer, PPI -> ID27 + * A legacy nFIQ, PPI -> ID28 + * Private timer, PPI -> ID29 + * Watchdog timers, PPI -> ID30 + * A legacy nIRQ, PPI -> ID31 + */ + gic_init(0, 27, MVF_IO_ADDRESS(MVF_INTD_BASE_ADDR), + MVF_IO_ADDRESS(MVF_SCUGIC_BASE_ADDR + 0x100)); + + mvf_register_gpios(); + + for (i = 0; i < 112; i++) + __raw_writew(1, int_router_base + 0x80 + 2 * i); +} diff --git a/arch/arm/mach-mvf/mm.c b/arch/arm/mach-mvf/mm.c new file mode 100644 index 000000000000..957398ccb8f5 --- /dev/null +++ b/arch/arm/mach-mvf/mm.c @@ -0,0 +1,89 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * Create static mapping between physical to virtual memory. + */ + +#include <linux/mm.h> +#include <linux/init.h> + +#include <asm/mach/map.h> +#include <mach/iomux-v3.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/iomux-v3.h> +#include <asm/hardware/cache-l2x0.h> +#include <mach/mvf.h> + +/*! + * This structure defines the MVF memory map. + */ +static struct map_desc mvf_io_desc[] __initdata = { + { + .virtual = (unsigned long)MVF_IO_ADDRESS(BOOT_ROM_BASE_ADDR), + .pfn = __phys_to_pfn(BOOT_ROM_BASE_ADDR), + .length = ROMCP_SIZE, + .type = MT_DEVICE}, + { + .virtual = (unsigned long)MVF_IO_ADDRESS(MVF_AIPS0_BASE_ADDR), + .pfn = __phys_to_pfn(MVF_AIPS0_BASE_ADDR), + .length = MVF_AIPS0_SIZE, + .type = MT_DEVICE}, + { + .virtual = (unsigned long)MVF_IO_ADDRESS(MVF_AIPS1_BASE_ADDR), + .pfn = __phys_to_pfn(MVF_AIPS1_BASE_ADDR), + .length = MVF_AIPS1_SIZE, + .type = MT_DEVICE}, +}; +/*! + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory map for + * the IO modules. + */ +void __init mvf_map_io(void) +{ + iotable_init(mvf_io_desc, ARRAY_SIZE(mvf_io_desc)); + mxc_iomux_v3_init(MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MVF_IO_ADDRESS(MVF_WDOG1_BASE_ADDR)); + mxc_set_cpu_type(MXC_CPU_MVF); +} +#ifdef CONFIG_CACHE_L2X0 +int mxc_init_l2x0(void) +{ + unsigned int val; + + writel(0x132, MVF_IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL)); + writel(0x132, MVF_IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL)); + + val = readl(MVF_IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); + val |= 0x40800000; + writel(val, MVF_IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); + val = readl(MVF_IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL)); + val |= L2X0_DYNAMIC_CLK_GATING_EN; + val |= L2X0_STNDBY_MODE_EN; + writel(val, MVF_IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL)); + + l2x0_init(MVF_IO_ADDRESS(L2_BASE_ADDR), 0x0, ~0x00000000); + return 0; +} + + +arch_initcall(mxc_init_l2x0); +#endif diff --git a/arch/arm/mach-mvf/regs-anadig.h b/arch/arm/mach-mvf/regs-anadig.h new file mode 100644 index 000000000000..4f37dfce14af --- /dev/null +++ b/arch/arm/mach-mvf/regs-anadig.h @@ -0,0 +1,1008 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * Freescale ANADIG Register Definitions + * + * Based on I.MX6 definitions + * + */ + +#ifndef __ARCH_ARM___ANADIG_H +#define __ARCH_ARM___ANADIG_H + + +#define HW_ANADIG_PLL_SYS (0x00000000) +#define HW_ANADIG_PLL_SYS_SET (0x00000004) +#define HW_ANADIG_PLL_SYS_CLR (0x00000008) +#define HW_ANADIG_PLL_SYS_TOG (0x0000000c) + +#define BM_ANADIG_PLL_SYS_LOCK 0x80000000 +#define BP_ANADIG_PLL_SYS_RSVD0 20 +#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 +#define BF_ANADIG_PLL_SYS_RSVD0(v) \ + (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) +#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 +#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 +#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 +#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 +#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 +#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 +#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F +#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) + +#define HW_ANADIG_USB1_PLL_480_CTRL (0x00000010) +#define HW_ANADIG_USB1_PLL_480_CTRL_SET (0x00000014) +#define HW_ANADIG_USB1_PLL_480_CTRL_CLR (0x00000018) +#define HW_ANADIG_USB1_PLL_480_CTRL_TOG (0x0000001c) + +#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 +#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 +#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 +#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ + (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 +#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 +#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 +#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 +#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 +#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 +#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C +#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ + (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) +#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 +#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 +#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) + +#define HW_ANADIG_USB2_PLL_480_CTRL (0x00000020) +#define HW_ANADIG_USB2_PLL_480_CTRL_SET (0x00000024) +#define HW_ANADIG_USB2_PLL_480_CTRL_CLR (0x00000028) +#define HW_ANADIG_USB2_PLL_480_CTRL_TOG (0x0000002c) + +#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK 0x80000000 +#define BP_ANADIG_USB2_PLL_480_CTRL_RSVD1 17 +#define BM_ANADIG_USB2_PLL_480_CTRL_RSVD1 0x7FFE0000 +#define BF_ANADIG_USB2_PLL_480_CTRL_RSVD1(v) \ + (((v) << 17) & BM_ANADIG_USB2_PLL_480_CTRL_RSVD1) +#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 +#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14 +#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 +#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP 0x00000400 +#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP 0x00000200 +#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF 0x00000100 +#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF 0x00000080 +#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 +#define BM_ANADIG_USB2_PLL_480_CTRL_RSVD0 0x00000020 +#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2 +#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 0x0000001C +#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) \ + (((v) << 2) & BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0) +#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0 +#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0x00000003 +#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) + +#define HW_ANADIG_PLL_528 (0x00000030) +#define HW_ANADIG_PLL_528_SET (0x00000034) +#define HW_ANADIG_PLL_528_CLR (0x00000038) +#define HW_ANADIG_PLL_528_TOG (0x0000003c) + +#define BM_ANADIG_PLL_528_LOCK 0x80000000 +#define BP_ANADIG_PLL_528_RSVD1 19 +#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 +#define BF_ANADIG_PLL_528_RSVD1(v) \ + (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) +#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_528_BYPASS 0x00010000 +#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_528_ENABLE 0x00002000 +#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_528_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_528_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_528_RSVD0 1 +#define BM_ANADIG_PLL_528_RSVD0 0x0000007E +#define BF_ANADIG_PLL_528_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) +#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 + +#define HW_ANADIG_PLL_528_SS (0x00000040) + +#define BP_ANADIG_PLL_528_SS_STOP 16 +#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 +#define BF_ANADIG_PLL_528_SS_STOP(v) \ + (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) +#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 +#define BP_ANADIG_PLL_528_SS_STEP 0 +#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF +#define BF_ANADIG_PLL_528_SS_STEP(v) \ + (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) + +#define HW_ANADIG_PLL_528_NUM (0x00000050) + +#define BP_ANADIG_PLL_528_NUM_RSVD0 30 +#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) +#define BP_ANADIG_PLL_528_NUM_A 0 +#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_528_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) + +#define HW_ANADIG_PLL_528_DENOM (0x00000060) + +#define BP_ANADIG_PLL_528_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) +#define BP_ANADIG_PLL_528_DENOM_B 0 +#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_528_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) + +#define HW_ANADIG_PLL_AUDIO (0x00000070) +#define HW_ANADIG_PLL_AUDIO_SET (0x00000074) +#define HW_ANADIG_PLL_AUDIO_CLR (0x00000078) +#define HW_ANADIG_PLL_AUDIO_TOG (0x0000007c) + +#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 +#define BP_ANADIG_PLL_AUDIO_RSVD0 22 +#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 +#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ + (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) +#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 +#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 +#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 +#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ + (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) +#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 +#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 +#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 +#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F +#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) + +#define HW_ANADIG_PLL_AUDIO_NUM (0x00000080) + +#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 +#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) +#define BP_ANADIG_PLL_AUDIO_NUM_A 0 +#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) + +#define HW_ANADIG_PLL_AUDIO_DENOM (0x00000090) + +#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) +#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 +#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) + +#define HW_ANADIG_PLL_VIDEO (0x000000a0) +#define HW_ANADIG_PLL_VIDEO_SET (0x000000a4) +#define HW_ANADIG_PLL_VIDEO_CLR (0x000000a8) +#define HW_ANADIG_PLL_VIDEO_TOG (0x000000ac) + +#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 +#define BP_ANADIG_PLL_VIDEO_RSVD0 22 +#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 +#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ + (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) +#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 +#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 +#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 +#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ + (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) +#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 +#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 +#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 +#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F +#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) + +#define HW_ANADIG_PLL_VIDEO_NUM (0x000000b0) + +#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 +#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) +#define BP_ANADIG_PLL_VIDEO_NUM_A 0 +#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ + (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) + +#define HW_ANADIG_PLL_VIDEO_DENOM (0x000000c0) + +#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 +#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 +#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ + (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) +#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 +#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ + (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) + +#define HW_ANADIG_PLL_MLB (0x000000d0) +#define HW_ANADIG_PLL_MLB_SET (0x000000d4) +#define HW_ANADIG_PLL_MLB_CLR (0x000000d8) +#define HW_ANADIG_PLL_MLB_TOG (0x000000dc) + +#define BM_ANADIG_PLL_MLB_LOCK 0x80000000 +#define BP_ANADIG_PLL_MLB_RSVD2 29 +#define BM_ANADIG_PLL_MLB_RSVD2 0x60000000 +#define BF_ANADIG_PLL_MLB_RSVD2(v) \ + (((v) << 29) & BM_ANADIG_PLL_MLB_RSVD2) +#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_SEL 26 +#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL 0x1C000000 +#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_SEL(v) \ + (((v) << 26) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL) +#define BP_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG 23 +#define BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG 0x03800000 +#define BF_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG(v) \ + (((v) << 23) & BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG) +#define BP_ANADIG_PLL_MLB_VDDD_DELAY_CFG 20 +#define BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG 0x00700000 +#define BF_ANADIG_PLL_MLB_VDDD_DELAY_CFG(v) \ + (((v) << 20) & BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG) +#define BP_ANADIG_PLL_MLB_VDDA_DELAY_CFG 17 +#define BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG 0x000E0000 +#define BF_ANADIG_PLL_MLB_VDDA_DELAY_CFG(v) \ + (((v) << 17) & BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG) +#define BM_ANADIG_PLL_MLB_BYPASS 0x00010000 +#define BP_ANADIG_PLL_MLB_RSVD1 14 +#define BM_ANADIG_PLL_MLB_RSVD1 0x0000C000 +#define BF_ANADIG_PLL_MLB_RSVD1(v) \ + (((v) << 14) & BM_ANADIG_PLL_MLB_RSVD1) +#define BP_ANADIG_PLL_MLB_PHASE_SEL 12 +#define BM_ANADIG_PLL_MLB_PHASE_SEL 0x00003000 +#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \ + (((v) << 12) & BM_ANADIG_PLL_MLB_PHASE_SEL) +#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_MLB_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_MLB_HALF_CP 0x00000200 +#define BP_ANADIG_PLL_MLB_RSVD0 0 +#define BM_ANADIG_PLL_MLB_RSVD0 0x000001FF +#define BF_ANADIG_PLL_MLB_RSVD0(v) \ + (((v) << 0) & BM_ANADIG_PLL_MLB_RSVD0) + +#define HW_ANADIG_PLL_ENET (0x000000e0) +#define HW_ANADIG_PLL_ENET_SET (0x000000e4) +#define HW_ANADIG_PLL_ENET_CLR (0x000000e8) +#define HW_ANADIG_PLL_ENET_TOG (0x000000ec) + +#define BM_ANADIG_PLL_ENET_LOCK 0x80000000 +#define BP_ANADIG_PLL_ENET_RSVD1 21 +#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 +#define BF_ANADIG_PLL_ENET_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) +#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 +#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 +#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 +#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 +#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 +#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 +#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ + (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 +#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 +#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 +#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 +#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 +#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 +#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 +#define BP_ANADIG_PLL_ENET_RSVD0 2 +#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C +#define BF_ANADIG_PLL_ENET_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) +#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 +#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 +#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ + (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) + +#define HW_ANADIG_PFD_480 (0x000000f0) +#define HW_ANADIG_PFD_480_SET (0x000000f4) +#define HW_ANADIG_PFD_480_CLR (0x000000f8) +#define HW_ANADIG_PFD_480_TOG (0x000000fc) + +#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 +#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 +#define BP_ANADIG_PFD_480_PFD3_FRAC 24 +#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 +#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ + (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) +#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 +#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 +#define BP_ANADIG_PFD_480_PFD2_FRAC 16 +#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 +#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ + (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) +#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 +#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 +#define BP_ANADIG_PFD_480_PFD1_FRAC 8 +#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 +#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ + (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) +#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 +#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 +#define BP_ANADIG_PFD_480_PFD0_FRAC 0 +#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F +#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ + (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) + +#define HW_ANADIG_PFD_528 (0x00000100) +#define HW_ANADIG_PFD_528_SET (0x00000104) +#define HW_ANADIG_PFD_528_CLR (0x00000108) +#define HW_ANADIG_PFD_528_TOG (0x0000010c) + +#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 +#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 +#define BP_ANADIG_PFD_528_PFD3_FRAC 24 +#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 +#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ + (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) +#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 +#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 +#define BP_ANADIG_PFD_528_PFD2_FRAC 16 +#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 +#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ + (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) +#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 +#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 +#define BP_ANADIG_PFD_528_PFD1_FRAC 8 +#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 +#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ + (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) +#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 +#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 +#define BP_ANADIG_PFD_528_PFD0_FRAC 0 +#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F +#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ + (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) + +#define HW_ANADIG_REG_1P1 (0x00000110) +#define HW_ANADIG_REG_1P1_SET (0x00000114) +#define HW_ANADIG_REG_1P1_CLR (0x00000118) +#define HW_ANADIG_REG_1P1_TOG (0x0000011c) + +#define BP_ANADIG_REG_1P1_RSVD2 18 +#define BM_ANADIG_REG_1P1_RSVD2 0xFFFC0000 +#define BF_ANADIG_REG_1P1_RSVD2(v) \ + (((v) << 18) & BM_ANADIG_REG_1P1_RSVD2) +#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000 +#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000 +#define BP_ANADIG_REG_1P1_RSVD1 13 +#define BM_ANADIG_REG_1P1_RSVD1 0x0000E000 +#define BF_ANADIG_REG_1P1_RSVD1(v) \ + (((v) << 13) & BM_ANADIG_REG_1P1_RSVD1) +#define BP_ANADIG_REG_1P1_OUTPUT_TRG 8 +#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x00001F00 +#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v) \ + (((v) << 8) & BM_ANADIG_REG_1P1_OUTPUT_TRG) +#define BM_ANADIG_REG_1P1_RSVD0 0x00000080 +#define BP_ANADIG_REG_1P1_BO_OFFSET 4 +#define BM_ANADIG_REG_1P1_BO_OFFSET 0x00000070 +#define BF_ANADIG_REG_1P1_BO_OFFSET(v) \ + (((v) << 4) & BM_ANADIG_REG_1P1_BO_OFFSET) +#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008 +#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004 +#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002 +#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001 + +#define HW_ANADIG_REG_3P0 (0x00000120) +#define HW_ANADIG_REG_3P0_SET (0x00000124) +#define HW_ANADIG_REG_3P0_CLR (0x00000128) +#define HW_ANADIG_REG_3P0_TOG (0x0000012c) + +#define BP_ANADIG_REG_3P0_RSVD2 18 +#define BM_ANADIG_REG_3P0_RSVD2 0xFFFC0000 +#define BF_ANADIG_REG_3P0_RSVD2(v) \ + (((v) << 18) & BM_ANADIG_REG_3P0_RSVD2) +#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000 +#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000 +#define BP_ANADIG_REG_3P0_RSVD1 13 +#define BM_ANADIG_REG_3P0_RSVD1 0x0000E000 +#define BF_ANADIG_REG_3P0_RSVD1(v) \ + (((v) << 13) & BM_ANADIG_REG_3P0_RSVD1) +#define BP_ANADIG_REG_3P0_OUTPUT_TRG 8 +#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x00001F00 +#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v) \ + (((v) << 8) & BM_ANADIG_REG_3P0_OUTPUT_TRG) +#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080 +#define BP_ANADIG_REG_3P0_BO_OFFSET 4 +#define BM_ANADIG_REG_3P0_BO_OFFSET 0x00000070 +#define BF_ANADIG_REG_3P0_BO_OFFSET(v) \ + (((v) << 4) & BM_ANADIG_REG_3P0_BO_OFFSET) +#define BM_ANADIG_REG_3P0_RSVD0 0x00000008 +#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004 +#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002 +#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001 + +#define HW_ANADIG_REG_2P5 (0x00000130) +#define HW_ANADIG_REG_2P5_SET (0x00000134) +#define HW_ANADIG_REG_2P5_CLR (0x00000138) +#define HW_ANADIG_REG_2P5_TOG (0x0000013c) + +#define BP_ANADIG_REG_2P5_RSVD2 19 +#define BM_ANADIG_REG_2P5_RSVD2 0xFFF80000 +#define BF_ANADIG_REG_2P5_RSVD2(v) \ + (((v) << 19) & BM_ANADIG_REG_2P5_RSVD2) +#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000 +#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000 +#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000 +#define BP_ANADIG_REG_2P5_RSVD1 13 +#define BM_ANADIG_REG_2P5_RSVD1 0x0000E000 +#define BF_ANADIG_REG_2P5_RSVD1(v) \ + (((v) << 13) & BM_ANADIG_REG_2P5_RSVD1) +#define BP_ANADIG_REG_2P5_OUTPUT_TRG 8 +#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x00001F00 +#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v) \ + (((v) << 8) & BM_ANADIG_REG_2P5_OUTPUT_TRG) +#define BM_ANADIG_REG_2P5_RSVD0 0x00000080 +#define BP_ANADIG_REG_2P5_BO_OFFSET 4 +#define BM_ANADIG_REG_2P5_BO_OFFSET 0x00000070 +#define BF_ANADIG_REG_2P5_BO_OFFSET(v) \ + (((v) << 4) & BM_ANADIG_REG_2P5_BO_OFFSET) +#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008 +#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004 +#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002 +#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001 + +#define HW_ANADIG_REG_CORE (0x00000140) +#define HW_ANADIG_REG_CORE_SET (0x00000144) +#define HW_ANADIG_REG_CORE_CLR (0x00000148) +#define HW_ANADIG_REG_CORE_TOG (0x0000014c) + +#define BM_ANADIG_REG_CORE_REF_SHIFT 0x80000000 +#define BM_ANADIG_REG_CORE_RSVD0 0x40000000 +#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 +#define BP_ANADIG_REG_CORE_RAMP_RATE 27 +#define BM_ANADIG_REG_CORE_RAMP_RATE 0x18000000 +#define BF_ANADIG_REG_CORE_RAMP_RATE(v) \ + (((v) << 27) & BM_ANADIG_REG_CORE_RAMP_RATE) +#define BP_ANADIG_REG_CORE_REG2_ADJ 23 +#define BM_ANADIG_REG_CORE_REG2_ADJ 0x07800000 +#define BF_ANADIG_REG_CORE_REG2_ADJ(v) \ + (((v) << 23) & BM_ANADIG_REG_CORE_REG2_ADJ) +#define BP_ANADIG_REG_CORE_REG2_TRG 18 +#define BM_ANADIG_REG_CORE_REG2_TRG 0x007C0000 +#define BF_ANADIG_REG_CORE_REG2_TRG(v) \ + (((v) << 18) & BM_ANADIG_REG_CORE_REG2_TRG) +#define BP_ANADIG_REG_CORE_REG1_ADJ 14 +#define BM_ANADIG_REG_CORE_REG1_ADJ 0x0003C000 +#define BF_ANADIG_REG_CORE_REG1_ADJ(v) \ + (((v) << 14) & BM_ANADIG_REG_CORE_REG1_ADJ) +#define BP_ANADIG_REG_CORE_REG1_TRG 9 +#define BM_ANADIG_REG_CORE_REG1_TRG 0x00003E00 +#define BF_ANADIG_REG_CORE_REG1_TRG(v) \ + (((v) << 9) & BM_ANADIG_REG_CORE_REG1_TRG) +#define BP_ANADIG_REG_CORE_REG0_ADJ 5 +#define BM_ANADIG_REG_CORE_REG0_ADJ 0x000001E0 +#define BF_ANADIG_REG_CORE_REG0_ADJ(v) \ + (((v) << 5) & BM_ANADIG_REG_CORE_REG0_ADJ) +#define BP_ANADIG_REG_CORE_REG0_TRG 0 +#define BM_ANADIG_REG_CORE_REG0_TRG 0x0000001F +#define BF_ANADIG_REG_CORE_REG0_TRG(v) \ + (((v) << 0) & BM_ANADIG_REG_CORE_REG0_TRG) + +#define HW_ANADIG_ANA_MISC0 (0x00000150) +#define HW_ANADIG_ANA_MISC0_SET (0x00000154) +#define HW_ANADIG_ANA_MISC0_CLR (0x00000158) +#define HW_ANADIG_ANA_MISC0_TOG (0x0000015c) + +#define BP_ANADIG_ANA_MISC0_RSVD2 29 +#define BM_ANADIG_ANA_MISC0_RSVD2 0xE0000000 +#define BF_ANADIG_ANA_MISC0_RSVD2(v) \ + (((v) << 29) & BM_ANADIG_ANA_MISC0_RSVD2) +#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26 +#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000 +#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \ + (((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY) +#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000 +#define BP_ANADIG_ANA_MISC0_ANAMUX 21 +#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000 +#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \ + (((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX) +#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000 +#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18 +#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000 +#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \ + (((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000 +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000 +#define BP_ANADIG_ANA_MISC0_OSC_I 14 +#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000 +#define BF_ANADIG_ANA_MISC0_OSC_I(v) \ + (((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I) +#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN 0x00002000 +#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000 +#define BP_ANADIG_ANA_MISC0_RSVD0 10 +#define BM_ANADIG_ANA_MISC0_RSVD0 0x00000C00 +#define BF_ANADIG_ANA_MISC0_RSVD0(v) \ + (((v) << 10) & BM_ANADIG_ANA_MISC0_RSVD0) +#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8 +#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300 +#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \ + (((v) << 8) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080 +#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4 +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x00000070 +#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \ + (((v) << 4) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ) +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 +#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004 +#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002 +#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001 + +#define HW_ANADIG_ANA_MISC1 (0x00000160) +#define HW_ANADIG_ANA_MISC1_SET (0x00000164) +#define HW_ANADIG_ANA_MISC1_CLR (0x00000168) +#define HW_ANADIG_ANA_MISC1_TOG (0x0000016c) + +#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO 0x80000000 +#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000 +#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000 +#define BP_ANADIG_ANA_MISC1_RSVD0 14 +#define BM_ANADIG_ANA_MISC1_RSVD0 0x1FFFC000 +#define BF_ANADIG_ANA_MISC1_RSVD0(v) \ + (((v) << 14) & BM_ANADIG_ANA_MISC1_RSVD0) +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN 0x00002000 +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000 +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN 0x00000800 +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400 +#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5 +#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0 +#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \ + (((v) << 5) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) +#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0 +#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F +#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \ + (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) + +#define HW_ANADIG_ANA_MISC2 (0x00000170) +#define HW_ANADIG_ANA_MISC2_SET (0x00000174) +#define HW_ANADIG_ANA_MISC2_CLR (0x00000178) +#define HW_ANADIG_ANA_MISC2_TOG (0x0000017c) + +#define BP_ANADIG_ANA_MISC2_CONTROL3 30 +#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000 +#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \ + (((v) << 30) & BM_ANADIG_ANA_MISC2_CONTROL3) +#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28 +#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000 +#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \ + (((v) << 28) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME) +#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26 +#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000 +#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \ + (((v) << 26) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME) +#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24 +#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000 +#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \ + (((v) << 24) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME) +#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000 +#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000 +#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO 0x00200000 +#define BM_ANADIG_ANA_MISC2_RSVD2 0x00100000 +#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS 0x00080000 +#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16 +#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000 +#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \ + (((v) << 16) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET) +#define BM_ANADIG_ANA_MISC2_CONTROL1 0x00008000 +#define BM_ANADIG_ANA_MISC2_REG1_OK 0x00004000 +#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO 0x00002000 +#define BM_ANADIG_ANA_MISC2_RSVD1 0x00001000 +#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS 0x00000800 +#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8 +#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700 +#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \ + (((v) << 8) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET) +#define BM_ANADIG_ANA_MISC2_CONTROL0 0x00000080 +#define BM_ANADIG_ANA_MISC2_REG0_OK 0x00000040 +#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO 0x00000020 +#define BM_ANADIG_ANA_MISC2_RSVD0 0x00000010 +#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS 0x00000008 +#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0 +#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0x00000007 +#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \ + (((v) << 0) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET) + +#define HW_ANADIG_TEMPSENSE0 (0x00000180) +#define HW_ANADIG_TEMPSENSE0_SET (0x00000184) +#define HW_ANADIG_TEMPSENSE0_CLR (0x00000188) +#define HW_ANADIG_TEMPSENSE0_TOG (0x0000018c) + +#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20 +#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000 +#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \ + (((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE) +#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8 +#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00 +#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \ + (((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) +#define BM_ANADIG_TEMPSENSE0_RSVD0 0x00000080 +#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040 +#define BP_ANADIG_TEMPSENSE0_VBGADJ 3 +#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038 +#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \ + (((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ) +#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004 +#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002 +#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001 + +#define HW_ANADIG_TEMPSENSE1 (0x00000190) +#define HW_ANADIG_TEMPSENSE1_SET (0x00000194) +#define HW_ANADIG_TEMPSENSE1_CLR (0x00000198) +#define HW_ANADIG_TEMPSENSE1_TOG (0x0000019c) + +#define BP_ANADIG_TEMPSENSE1_RSVD0 16 +#define BM_ANADIG_TEMPSENSE1_RSVD0 0xFFFF0000 +#define BF_ANADIG_TEMPSENSE1_RSVD0(v) \ + (((v) << 16) & BM_ANADIG_TEMPSENSE1_RSVD0) +#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0 +#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF +#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \ + (((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ) + +#define HW_ANADIG_USB1_VBUS_DETECT (0x000001a0) +#define HW_ANADIG_USB1_VBUS_DETECT_SET (0x000001a4) +#define HW_ANADIG_USB1_VBUS_DETECT_CLR (0x000001a8) +#define HW_ANADIG_USB1_VBUS_DETECT_TOG (0x000001ac) + +#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD2 28 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD2 0x70000000 +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD2(v) \ + (((v) << 28) & BM_ANADIG_USB1_VBUS_DETECT_RSVD2) +#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000 +#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD1 21 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD1 0x03E00000 +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_USB1_VBUS_DETECT_RSVD1) +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD0 8 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD0 0x0003FF00 +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD0(v) \ + (((v) << 8) & BM_ANADIG_USB1_VBUS_DETECT_RSVD0) +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080 +#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040 +#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020 +#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008 +#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 +#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v) \ + (((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH) + +#define HW_ANADIG_USB1_CHRG_DETECT (0x000001b0) +#define HW_ANADIG_USB1_CHRG_DETECT_SET (0x000001b4) +#define HW_ANADIG_USB1_CHRG_DETECT_CLR (0x000001b8) +#define HW_ANADIG_USB1_CHRG_DETECT_TOG (0x000001bc) + +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD2 24 +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD2 0xFF000000 +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD2(v) \ + (((v) << 24) & BM_ANADIG_USB1_CHRG_DETECT_RSVD2) +#define BM_ANADIG_USB1_CHRG_DETECT_BGR_BIAS 0x00800000 +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD1 21 +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD1 0x00600000 +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_USB1_CHRG_DETECT_RSVD1) +#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000 +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD0 1 +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD0 0x0003FFFE +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_USB1_CHRG_DETECT_RSVD0) +#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001 + +#define HW_ANADIG_USB1_VBUS_DET_STAT (0x000001c0) +#define HW_ANADIG_USB1_VBUS_DET_STAT_SET (0x000001c4) +#define HW_ANADIG_USB1_VBUS_DET_STAT_CLR (0x000001c8) +#define HW_ANADIG_USB1_VBUS_DET_STAT_TOG (0x000001cc) + +#define BP_ANADIG_USB1_VBUS_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB1_VBUS_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0) +#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008 +#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004 +#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002 +#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001 + +#define HW_ANADIG_USB1_CHRG_DET_STAT (0x000001d0) +#define HW_ANADIG_USB1_CHRG_DET_STAT_SET (0x000001d4) +#define HW_ANADIG_USB1_CHRG_DET_STAT_CLR (0x000001d8) +#define HW_ANADIG_USB1_CHRG_DET_STAT_TOG (0x000001dc) + +#define BP_ANADIG_USB1_CHRG_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB1_CHRG_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0) +#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008 +#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004 +#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 +#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 + +#define HW_ANADIG_USB1_LOOPBACK (0x000001e0) +#define HW_ANADIG_USB1_LOOPBACK_SET (0x000001e4) +#define HW_ANADIG_USB1_LOOPBACK_CLR (0x000001e8) +#define HW_ANADIG_USB1_LOOPBACK_TOG (0x000001ec) + +#define BP_ANADIG_USB1_LOOPBACK_RSVD0 9 +#define BM_ANADIG_USB1_LOOPBACK_RSVD0 0xFFFFFE00 +#define BF_ANADIG_USB1_LOOPBACK_RSVD0(v) \ + (((v) << 9) & BM_ANADIG_USB1_LOOPBACK_RSVD0) +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100 +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004 +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002 +#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001 + +#define HW_ANADIG_USB1_MISC (0x000001f0) +#define HW_ANADIG_USB1_MISC_SET (0x000001f4) +#define HW_ANADIG_USB1_MISC_CLR (0x000001f8) +#define HW_ANADIG_USB1_MISC_TOG (0x000001fc) + +#define BM_ANADIG_USB1_MISC_RSVD1 0x80000000 +#define BM_ANADIG_USB1_MISC_EN_CLK_UTMI 0x40000000 +#define BM_ANADIG_USB1_MISC_RX_VPIN_FS 0x20000000 +#define BM_ANADIG_USB1_MISC_RX_VMIN_FS 0x10000000 +#define BM_ANADIG_USB1_MISC_RX_RXD_FS 0x08000000 +#define BM_ANADIG_USB1_MISC_RX_SQUELCH 0x04000000 +#define BM_ANADIG_USB1_MISC_RX_DISCON_DET 0x02000000 +#define BM_ANADIG_USB1_MISC_RX_HS_DATA 0x01000000 +#define BP_ANADIG_USB1_MISC_RSVD0 2 +#define BM_ANADIG_USB1_MISC_RSVD0 0x00FFFFFC +#define BF_ANADIG_USB1_MISC_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_USB1_MISC_RSVD0) +#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002 +#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001 + +#define HW_ANADIG_USB2_VBUS_DETECT (0x00000200) +#define HW_ANADIG_USB2_VBUS_DETECT_SET (0x00000204) +#define HW_ANADIG_USB2_VBUS_DETECT_CLR (0x00000208) +#define HW_ANADIG_USB2_VBUS_DETECT_TOG (0x0000020c) + +#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD2 28 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD2 0x70000000 +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD2(v) \ + (((v) << 28) & BM_ANADIG_USB2_VBUS_DETECT_RSVD2) +#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000 +#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD1 21 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD1 0x03E00000 +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_USB2_VBUS_DETECT_RSVD1) +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD0 3 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD0 0x0003FFF8 +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD0(v) \ + (((v) << 3) & BM_ANADIG_USB2_VBUS_DETECT_RSVD0) +#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0 +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 +#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v) \ + (((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH) + +#define HW_ANADIG_USB2_CHRG_DETECT (0x00000210) +#define HW_ANADIG_USB2_CHRG_DETECT_SET (0x00000214) +#define HW_ANADIG_USB2_CHRG_DETECT_CLR (0x00000218) +#define HW_ANADIG_USB2_CHRG_DETECT_TOG (0x0000021c) + +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD2 24 +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD2 0xFF000000 +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD2(v) \ + (((v) << 24) & BM_ANADIG_USB2_CHRG_DETECT_RSVD2) +#define BM_ANADIG_USB2_CHRG_DETECT_BGR_BIAS 0x00800000 +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD1 21 +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD1 0x00600000 +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_USB2_CHRG_DETECT_RSVD1) +#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000 +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD0 1 +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD0 0x0003FFFE +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_USB2_CHRG_DETECT_RSVD0) +#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001 + +#define HW_ANADIG_USB2_VBUS_DET_STAT (0x00000220) +#define HW_ANADIG_USB2_VBUS_DET_STAT_SET (0x00000224) +#define HW_ANADIG_USB2_VBUS_DET_STAT_CLR (0x00000228) +#define HW_ANADIG_USB2_VBUS_DET_STAT_TOG (0x0000022c) + +#define BP_ANADIG_USB2_VBUS_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB2_VBUS_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0) +#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008 +#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004 +#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002 +#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001 + +#define HW_ANADIG_USB2_CHRG_DET_STAT (0x00000230) +#define HW_ANADIG_USB2_CHRG_DET_STAT_SET (0x00000234) +#define HW_ANADIG_USB2_CHRG_DET_STAT_CLR (0x00000238) +#define HW_ANADIG_USB2_CHRG_DET_STAT_TOG (0x0000023c) + +#define BP_ANADIG_USB2_CHRG_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB2_CHRG_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0) +#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008 +#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004 +#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 +#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 + +#define HW_ANADIG_USB2_LOOPBACK (0x00000240) +#define HW_ANADIG_USB2_LOOPBACK_SET (0x00000244) +#define HW_ANADIG_USB2_LOOPBACK_CLR (0x00000248) +#define HW_ANADIG_USB2_LOOPBACK_TOG (0x0000024c) + +#define BP_ANADIG_USB2_LOOPBACK_RSVD0 9 +#define BM_ANADIG_USB2_LOOPBACK_RSVD0 0xFFFFFE00 +#define BF_ANADIG_USB2_LOOPBACK_RSVD0(v) \ + (((v) << 9) & BM_ANADIG_USB2_LOOPBACK_RSVD0) +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100 +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004 +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002 +#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001 + +#define HW_ANADIG_USB2_MISC (0x00000250) +#define HW_ANADIG_USB2_MISC_SET (0x00000254) +#define HW_ANADIG_USB2_MISC_CLR (0x00000258) +#define HW_ANADIG_USB2_MISC_TOG (0x0000025c) + +#define BM_ANADIG_USB2_MISC_RSVD1 0x80000000 +#define BM_ANADIG_USB2_MISC_EN_CLK_UTMI 0x40000000 +#define BM_ANADIG_USB2_MISC_RX_VPIN_FS 0x20000000 +#define BM_ANADIG_USB2_MISC_RX_VMIN_FS 0x10000000 +#define BM_ANADIG_USB2_MISC_RX_RXD_FS 0x08000000 +#define BM_ANADIG_USB2_MISC_RX_SQUELCH 0x04000000 +#define BM_ANADIG_USB2_MISC_RX_DISCON_DET 0x02000000 +#define BM_ANADIG_USB2_MISC_RX_HS_DATA 0x01000000 +#define BP_ANADIG_USB2_MISC_RSVD0 2 +#define BM_ANADIG_USB2_MISC_RSVD0 0x00FFFFFC +#define BF_ANADIG_USB2_MISC_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_USB2_MISC_RSVD0) +#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002 +#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001 + +#define HW_ANADIG_DIGPROG (0x00000260) + +#define BP_ANADIG_DIGPROG_RSVD 24 +#define BM_ANADIG_DIGPROG_RSVD 0xFF000000 +#define BF_ANADIG_DIGPROG_RSVD(v) \ + (((v) << 24) & BM_ANADIG_DIGPROG_RSVD) +#define BP_ANADIG_DIGPROG_MAJOR 8 +#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00 +#define BF_ANADIG_DIGPROG_MAJOR(v) \ + (((v) << 8) & BM_ANADIG_DIGPROG_MAJOR) +#define BP_ANADIG_DIGPROG_MINOR 0 +#define BM_ANADIG_DIGPROG_MINOR 0x000000FF +#define BF_ANADIG_DIGPROG_MINOR(v) \ + (((v) << 0) & BM_ANADIG_DIGPROG_MINOR) +#endif /* __ARCH_ARM___ANADIG_H */ diff --git a/arch/arm/mach-mvf/system.c b/arch/arm/mach-mvf/system.c new file mode 100644 index 000000000000..764c608cbf42 --- /dev/null +++ b/arch/arm/mach-mvf/system.c @@ -0,0 +1,36 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/pmic_external.h> +#include <asm/io.h> +#include <mach/hardware.h> +#include <mach/clock.h> +#include <asm/proc-fns.h> +#include <asm/system.h> +#include "crm_regs.h" +#include "regs-anadig.h" + +void arch_idle(void) +{ + cpu_do_idle(); +} |