diff options
author | Pedro Perez de Heredia <pedro.perez@digi.com> | 2010-11-20 20:42:33 +0100 |
---|---|---|
committer | Alejandro Gonzalez <alex.gonzalez@digi.com> | 2011-01-21 15:45:15 +0100 |
commit | 9368081a3b1e7a20418fbc923871a941c8178bfe (patch) | |
tree | 7a2c40b8f3e6992098ba0a03a28eeab4b2859888 /arch/arm/mach-mx5/clock.c | |
parent | 7b0c8adf1fa01079d6c174b1fa42bf5f3cb5a385 (diff) |
ccmwx51: workaround random crash at boot time
This commit modifies the code that enables the cpu clock.
Instead of enabling that clock early in the clock configuration
sequence, it is enabled late.
The early enable was causing a random crash at boot time on the
ConnectCore Wi-i.MX51 for unknown reasons.
Enabling the cpu clock late, seems to work around the problem.
This issue have to be investigaged to better understand the
real cause of the problem and the real solution.
Signed-off-by: Pedro Perez de Heredia <pedro.perez@digi.com>
Diffstat (limited to 'arch/arm/mach-mx5/clock.c')
-rw-r--r-- | arch/arm/mach-mx5/clock.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index 6e71cba29795..648c1c01d3ba 100644 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -4503,7 +4503,10 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long reg |= MXC_CCM_CCDR_HSC_HS_MASK; __raw_writel(reg, MXC_CCM_CCDR); +#ifndef CONFIG_LATE_CPU_CLK_ENABLE + /* See comment below where cpu_clk is enabled for further information */ clk_enable(&cpu_clk); +#endif /* Set SDHC parents to be PLL2 */ clk_set_parent(&esdhc1_clk[0], &pll2_sw_clk); @@ -4680,6 +4683,15 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long base = ioremap(GPT1_BASE_ADDR, SZ_4K); mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); +#ifdef CONFIG_LATE_CPU_CLK_ENABLE + /** + * Late enable of the cpu clock. This is causing a random crash at boot + * time on the ConnectCore Wi-i.MX51. Enabling the cpu clock here seems + * to work around the problem. Must be in order to better understand the + * reason of the problem and the real solution to the problem. + */ + clk_enable(&cpu_clk); +#endif return 0; } |