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authorXinyu Chen <xinyu.chen@freescale.com>2011-03-29 15:35:52 +0800
committerAlex Gonzalez <alex.gonzalez@digi.com>2011-08-01 09:51:23 +0200
commit96057c315c4c314b11c0663d4587e70f40debab1 (patch)
treea17f9f862c6de50b8ba03654441441dd12a34136 /arch/arm/mach-mx5/clock.c
parentcb0e46f73f800b5a9d40a149684565c700c552d3 (diff)
ENGR00141310 mx5x clock: add emi_fast_clk as tz1's parent for uart dma
UART dma mode doing data transfer between uart fifo and ddr. So emi_fast_clk must be enabled when dma on. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com> Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'arch/arm/mach-mx5/clock.c')
-rw-r--r--arch/arm/mach-mx5/clock.c24
1 files changed, 15 insertions, 9 deletions
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index 17e21017d9b3..4ccecb9683fa 100644
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -1342,13 +1342,19 @@ static struct clk ocram_clk = {
};
-static struct clk aips_tz1_clk = {
- .parent = &ahb_clk,
- .secondary = &ahb_max_clk,
- .enable_reg = MXC_CCM_CCGR0,
- .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
- .enable = _clk_enable,
- .disable = _clk_disable_inwait,
+static struct clk aips_tz1_clk[] = {
+ {
+ .parent = &ahb_clk,
+ .secondary = &aips_tz1_clk[1],
+ .enable_reg = MXC_CCM_CCGR0,
+ .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable_inwait,
+ },
+ {
+ .parent = &emi_fast_clk,
+ .secondary = &ahb_max_clk,
+ },
};
static struct clk aips_tz2_clk = {
@@ -2109,7 +2115,7 @@ static struct clk uart1_clk[] = {
.id = 0,
.parent = &ipg_clk,
#if UART1_DMA_ENABLE
- .secondary = &aips_tz1_clk,
+ .secondary = &aips_tz1_clk[0],
#endif
.enable_reg = MXC_CCM_CCGR1,
.enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
@@ -2135,7 +2141,7 @@ static struct clk uart2_clk[] = {
.id = 1,
.parent = &ipg_clk,
#if UART2_DMA_ENABLE
- .secondary = &aips_tz1_clk,
+ .secondary = &aips_tz1_clk[0],
#endif
.enable_reg = MXC_CCM_CCGR1,
.enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,