diff options
| author | Justin Waters <justin.waters@timesys.com> | 2010-05-18 10:10:26 -0400 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2010-05-18 10:10:26 -0400 |
| commit | 2e70c9f0621b65a563ba6961310ad7de9c6b4052 (patch) | |
| tree | 63d99c5c390cecaa252eac3ee0b746cebbe2c1ce /arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c | |
| parent | 63144b093aae08e3f573545326586b07f0d1cf95 (diff) | |
Add support for SDIO Wireless chip on the CCWMX51JS2.6.31-ccwmx51js-201005181410
Diffstat (limited to 'arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c')
| -rw-r--r-- | arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c b/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c index 293c9aa9545f..5d6d5def4566 100644 --- a/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c +++ b/arch/arm/mach-mx51/mx51_ccwmx51js_gpio.c @@ -332,6 +332,43 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { MX51_PIN_GPIO1_0, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION, (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), }, + /* SDHC2*/ +#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) + { + MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0, + (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0, + (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0, + (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0, + (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0, + (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_GPIO1_1, IOMUX_CONFIG_GPIO, + (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), + }, +#endif /* SDHC3 */ { MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION, |