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authorSammy He <r62914@freescale.com>2011-06-22 00:08:22 +0800
committerJason Liu <r64343@freescale.com>2012-07-20 13:14:02 +0800
commit56bbaf6a029def931cbce0f7e5d41283e93f1550 (patch)
tree4242ed8b6dd8ade559864bf17ff7bf7a55ba1c0b /arch/arm/mach-mx5
parentee653f33a617399adb76f5534dea0e67fcb7c04f (diff)
ENGR00151762 vpu: Fix system hang due to long time video playback on mx51
Fix system hang due to long time video playback. This issue is only on i.MX51 platfrom due to changing vpu clock parent in vpu_enable/ disable. Set vpu clock parent to axi_a forever to fix it. Signed-off-by: Sammy He <r62914@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx5')
-rwxr-xr-xarch/arm/mach-mx5/clock.c34
1 files changed, 4 insertions, 30 deletions
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index 4ffe416fc816..8f0d22a46dae 100755
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -3985,32 +3985,6 @@ static int _clk_vpu_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
-static int _clk_vpu_enable(struct clk *clk)
-{
- /* Set VPU's parent to be axi_a or ahb when its enabled. */
- if (cpu_is_mx51() && (mx51_revision() < IMX_CHIP_REVISION_2_0)) {
- clk_set_parent(&vpu_clk[0], &ahb_clk);
- clk_set_parent(&vpu_clk[1], &ahb_clk);
- } else if (cpu_is_mx51()) {
- clk_set_parent(&vpu_clk[0], &axi_a_clk);
- clk_set_parent(&vpu_clk[1], &axi_a_clk);
- }
-
- return _clk_enable(clk);
-
-}
-
-static void _clk_vpu_disable(struct clk *clk)
-{
- _clk_disable(clk);
-
- /* Set VPU's parent to be axi_b when its disabled. */
- if (cpu_is_mx51()) {
- clk_set_parent(&vpu_clk[0], &axi_b_clk);
- clk_set_parent(&vpu_clk[1], &axi_b_clk);
- }
-}
-
static struct clk vpu_clk[] = {
{
__INIT_CLK_DEBUG(vpu_clk_0)
@@ -4025,10 +3999,10 @@ static struct clk vpu_clk[] = {
{
__INIT_CLK_DEBUG(vpu_clk_1)
.set_parent = _clk_vpu_set_parent,
- .enable = _clk_vpu_enable,
+ .enable = _clk_enable,
.enable_reg = MXC_CCM_CCGR5,
.enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
- .disable = _clk_vpu_disable,
+ .disable = _clk_disable,
.secondary = &vpu_clk[2],
},
{
@@ -4749,8 +4723,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
/* Initialise the parents to be axi_b, parents are set to
* axi_a when the clocks are enabled.
*/
- clk_set_parent(&vpu_clk[0], &axi_b_clk);
- clk_set_parent(&vpu_clk[1], &axi_b_clk);
+ clk_set_parent(&vpu_clk[0], &axi_a_clk);
+ clk_set_parent(&vpu_clk[1], &axi_a_clk);
clk_set_parent(&gpu3d_clk, &axi_a_clk);
clk_set_parent(&gpu2d_clk, &axi_a_clk);