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authorDanny Nold <dannynold@freescale.com>2011-05-02 12:35:05 -0500
committerJason Liu <r64343@freescale.com>2012-01-09 20:08:35 +0800
commit9f6432dbf52812b1f69b284e9cb6e1939d5ec0d0 (patch)
tree3160bbf769c7c3cd95d363d05b3ab3f972e60273 /arch/arm/mach-mx5
parent4ecc99beae287a78f94ca117f9302733f0338476 (diff)
ENGR00142954 - MSL clocks: correct APLL settings to prevent random PxP lockups
- Add appropriate bit settings to ANADIG_MISC to improve APLL signal integrity and prevent intermittent PxP lockups Signed-off-by: Danny Nold <dannynold@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx5')
-rwxr-xr-xarch/arm/mach-mx5/clock_mx50.c14
-rwxr-xr-xarch/arm/mach-mx5/crm_regs.h4
2 files changed, 16 insertions, 2 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c
index ff3b0eb0f771..446e1e2ff476 100755
--- a/arch/arm/mach-mx5/clock_mx50.c
+++ b/arch/arm/mach-mx5/clock_mx50.c
@@ -324,18 +324,28 @@ static struct clk ckil_clk = {
static int apll_enable(struct clk *clk)
{
- __raw_writel(1, apll_base + MXC_ANADIG_MISC_SET);
+ /* Set bit to flush multiple edges out of PLL vco */
+ __raw_writel(MXC_ANADIG_PLL_HOLD_RING_OFF,
+ apll_base + MXC_ANADIG_MISC_SET);
+
+ __raw_writel(MXC_ANADIG_PLL_POWERUP, apll_base + MXC_ANADIG_MISC_SET);
if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL)
& MXC_ANADIG_APLL_LOCK, 80000))
panic("apll_enable failed!\n");
+ /* Clear after relocking, then wait 10 us */
+ __raw_writel(MXC_ANADIG_PLL_HOLD_RING_OFF,
+ apll_base + MXC_ANADIG_MISC_CLR);
+
+ udelay(10);
+
return 0;
}
static void apll_disable(struct clk *clk)
{
- __raw_writel(1, apll_base + MXC_ANADIG_MISC_CLR);
+ __raw_writel(MXC_ANADIG_PLL_POWERUP, apll_base + MXC_ANADIG_MISC_CLR);
}
static unsigned long apll_get_rate(struct clk *clk)
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index 864cca86ba23..c32d19f6ddb9 100755
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -125,6 +125,10 @@
#define MXC_ANADIG_PFD4_STABLE (1 << 6)
#define MXC_ANADIG_PFD4_FRAC_OFFSET 0
+#define MXC_ANADIG_REF_SELFBIAS_OFF (1 << 20)
+#define MXC_ANADIG_PLL_HOLD_RING_OFF (1 << 7)
+#define MXC_ANADIG_PLL_POWERUP (1 << 0)
+
#define MXC_ANADIG_APLL_LOCK (1 << 31)
#define MXC_ANADIG_APLL_FORCE_LOCK (1 << 30)
#define MXC_ANADIG_PFD_DIS_OFFSET 16