diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-06-07 00:16:06 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-06-12 07:29:34 -0500 |
| commit | ca0bb4bd4a06977077e95cc5d8f053aafeb2140c (patch) | |
| tree | 6d3227aa995ead6e86a7066358ef1b9c48a93b50 /arch/arm/mach-mx6/bus_freq.c | |
| parent | 2c470b3be32919927af5e46e073be1222d7f284c (diff) | |
ENGR000212647 MX6 - Fix IPU and AXI default clock frequency
The max freq for IPU and AXI clocks is 264MHz. Hence source
IPU from mmdc_ch0 clock on MX6 to get maximum frequency.
And source AXI from periph_clk on for max freq.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/bus_freq.c')
| -rw-r--r-- | arch/arm/mach-mx6/bus_freq.c | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c index 74289931b23b..36a8190dd812 100644 --- a/arch/arm/mach-mx6/bus_freq.c +++ b/arch/arm/mach-mx6/bus_freq.c @@ -49,7 +49,6 @@ #define LPAPM_CLK 24000000 #define DDR_MED_CLK 400000000 #define DDR3_NORMAL_CLK 528000000 -#define AXI_CLK_RATE 270000000 #define GPC_PGC_GPU_PGCR_OFFSET 0x260 #define GPC_CNTR_OFFSET 0x0 @@ -92,9 +91,6 @@ struct timeval end_time; static int cpu_op_nr; static struct cpu_op *cpu_op_tbl; static struct clk *pll2_400; -static struct clk *axi_clk; -static struct clk *periph_clk; -static struct clk *pll3_540; static struct clk *cpu_clk; static unsigned int org_ldo; static struct clk *pll3; @@ -126,11 +122,6 @@ static void reduce_bus_freq_handler(struct work_struct *work) return; } - /* Set the axi_clk to be sourced from the periph_clk. - * So that its frequency can be lowered down to 50MHz - * or 24MHz as the case may be. */ - clk_set_parent(axi_clk, periph_clk); - clk_enable(pll3); if (lp_audio_freq) { @@ -239,16 +230,6 @@ int set_high_bus_freq(int high_bus_freq) } clk_enable(pll3); - if (clk_get_parent(axi_clk) != pll3_540) { - /* We need to set axi_clk to be sourced from PLL3_540MHz. */ - /* Ensure the divider is set to divide by 2 before changing the - * parent. */ - if (low_bus_freq_mode) - clk_set_rate(axi_clk, clk_get_rate(axi_clk) / 2); - clk_set_parent(axi_clk, pll3_540); - clk_set_rate(axi_clk, AXI_CLK_RATE); - } - /* Enable the PU LDO */ if (cpu_is_mx6q() && low_bus_freq_mode) { __raw_writel(org_ldo, ANADIG_REG_CORE); @@ -401,27 +382,6 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(cpu_clk); } - axi_clk = clk_get(NULL, "axi_clk"); - if (IS_ERR(axi_clk)) { - printk(KERN_DEBUG "%s: failed to get axi_clk\n", - __func__); - return PTR_ERR(axi_clk); - } - - periph_clk = clk_get(NULL, "periph_clk"); - if (IS_ERR(periph_clk)) { - printk(KERN_DEBUG "%s: failed to get periph_clk\n", - __func__); - return PTR_ERR(periph_clk); - } - - pll3_540 = clk_get(NULL, "pll3_pfd_540M"); - if (IS_ERR(pll3_540)) { - printk(KERN_DEBUG "%s: failed to get periph_clk\n", - __func__); - return PTR_ERR(pll3_540); - } - err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr); if (err) { printk(KERN_ERR |