diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-07-27 16:41:58 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-07-30 20:13:33 -0500 |
| commit | 51e5dcf9e8b61a0af97852769c4b7ae1c01951d3 (patch) | |
| tree | 0003418ed696f7b0e61509b43cb930bcace2c2da /arch/arm/mach-mx6/bus_freq.c | |
| parent | ba0ad582e921bb4208b75289f3ecc22f773feb6e (diff) | |
ENGR00218747 - MX6Q/MX6DL: WAIT mode support for MX6QTO1.2/MX6DLTO1.1
Add the new WAIT mode workaround added for MX6Q1.2 and MX6DLTO1.1.
A new bit is added to CCM_CGPR (bit 17). This bit needs to be
enabled for the WAIT mode fix to be active and needs to be disabled
before the system enters STOP mode with power gating enabled.
Fix WAIT mode bug when system is in low power IDLE mode:
In low power IDLE mode (AHB @ 24MHz), switch ARM to run from 24MHz
on MX6QTO1.1 and MX6DLTO1.0 chips when ARM core enters WAIT mode.
We still need to use the ARM:IPG_CLK ratio of 12:5. Since IPG_CLK
is at 12MHz, we need to run ARM below 28.8MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/bus_freq.c')
| -rw-r--r-- | arch/arm/mach-mx6/bus_freq.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c index b1a0af0f3d35..12dea1474d9a 100644 --- a/arch/arm/mach-mx6/bus_freq.c +++ b/arch/arm/mach-mx6/bus_freq.c @@ -78,6 +78,8 @@ void set_ddr_freq(int ddr_freq); extern int init_mmdc_settings(void); extern struct cpu_op *(*get_cpu_op)(int *op); extern int update_ddr_freq(int ddr_rate); +extern int chip_rev; +extern bool arm_mem_clked_in_wait; struct mutex bus_freq_mutex; @@ -128,7 +130,6 @@ static void reduce_bus_freq_handler(struct work_struct *work) if (!cpu_is_mx6sl()) { clk_enable(pll3); - if (lp_audio_freq) { /* Need to ensure that PLL2_PFD_400M is kept ON. */ clk_enable(pll2_400); @@ -149,6 +150,7 @@ static void reduce_bus_freq_handler(struct work_struct *work) if (med_bus_freq_mode) clk_disable(pll2_400); + clk_disable(pll3); } else { /* Set VDDSOC_CAP to 1.1V */ @@ -162,6 +164,8 @@ static void reduce_bus_freq_handler(struct work_struct *work) udelay(150); + arm_mem_clked_in_wait = true; + /* Set periph_clk to be sourced from OSC_CLK */ /* Set MMDC clk to 25MHz. */ /* First need to set the divider before changing the parent */ @@ -305,6 +309,12 @@ int set_high_bus_freq(int high_bus_freq) low_bus_freq_mode = 0; audio_bus_freq_mode = 0; + + /* Ensure that WAIT mode can be entered in high bus freq mode. */ + + if (cpu_is_mx6sl()) + arm_mem_clked_in_wait = false; + mutex_unlock(&bus_freq_mutex); return 0; |