diff options
| author | Anson Huang <b20788@freescale.com> | 2012-06-13 20:20:01 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2012-06-14 13:21:25 +0800 |
| commit | 4992c0eee72065d500342e4f38dea8549137f48c (patch) | |
| tree | 4eee6c5d6422ee570713d0b01c5d5ac92eb8d8eb /arch/arm/mach-mx6/clock.c | |
| parent | 294c61415c3a1ec03e2406d64c92a9232b8c65ec (diff) | |
ENGR00180919 [MX6]Update clock tree if BUS freq is changed
As DDR freq change is by modifying CCM register directly,
we need to update the clock tree as well, or the clock
tree will be broken. Also, we need to make sure the clock
rate counting is right.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock.c')
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 2f58ca3b882f..975f22cc2263 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -499,6 +499,9 @@ static void _clk_pll_disable(struct clk *clk) unsigned int reg; void __iomem *pllbase; + if ((arm_needs_pll2_400) && (clk == &pll2_528_bus_main_clk)) + return; + pllbase = _get_pll_base(clk); reg = __raw_readl(pllbase); @@ -520,6 +523,10 @@ static unsigned long _clk_pll1_main_get_rate(struct clk *clk) unsigned int div; unsigned long val; + /* If PLL1 is bypassed, its rate will be from OSC directly */ + if (__raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_BYPASS_MASK) + return clk_get_rate(clk->parent); + div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK; val = (clk_get_rate(clk->parent) * div) / 2; return val; @@ -5288,7 +5295,6 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* keep correct count. */ clk_enable(&cpu_clk); clk_enable(&periph_clk); - /* Disable un-necessary PFDs & PLLs */ if (pll2_pfd_400M.usecount == 0 && cpu_is_mx6q()) pll2_pfd_400M.disable(&pll2_pfd_400M); |