ENGR000212647 MX6 - Fix IPU and AXI default clock frequency

The max freq for IPU and AXI clocks is 264MHz. Hence source
IPU from mmdc_ch0 clock on MX6 to get maximum frequency.
And source AXI from periph_clk on for max freq.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

1 files changed, 6 insertions, 10 deletions

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index ed7174a12b71..2f58ca3b882f 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -5342,20 +5342,16 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 		/* on mx6dl gpu2d_axi_clk source from mmdc0 directly */
 		clk_set_parent(&gpu2d_axi_clk, &mmdc_ch0_axi_clk[0]);
 
+		clk_set_parent(&ipu1_clk, &pll2_pfd_400M);
 		/* pxp & epdc */
 		clk_set_parent(&ipu2_clk, &pll2_pfd_400M);
 		clk_set_rate(&ipu2_clk, 200000000);
-	} else if (cpu_is_mx6q())
-		/* Donot source IPU from MMDC clock, as it can be scaled. */
-		clk_set_parent(&ipu2_clk, &pll3_pfd_540M);
-
-	/* Donot source IPU from MMDC clock, as it can be scaled. */
-	clk_set_parent(&ipu1_clk, &pll3_pfd_540M);
+	} else if (cpu_is_mx6q()) {
+		clk_set_parent(&ipu2_clk, &mmdc_ch0_axi_clk[0]);
+		clk_set_parent(&ipu1_clk, &mmdc_ch0_axi_clk[0]);
+	}
 
-	/* set axi_clk parent to pll3_pfd_540M, don't source from
-	  * periph_clk as it can be scaled.
-	  */
-	clk_set_parent(&axi_clk, &pll3_pfd_540M);
+	clk_set_parent(&axi_clk, &periph_clk);
 	/* Need to keep PLL3_PFD_540M enabled until AXI is sourced from it. */
 	clk_enable(&axi_clk);