diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-02-02 05:32:32 -0600 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:22:00 +0800 |
| commit | d5c6d731a01d583298a2cf25fb691e4655f4d59f (patch) | |
| tree | cfa566809a61591e7fe1546854c25b6a0d0534b6 /arch/arm/mach-mx6/clock.c | |
| parent | fe9485f328b3845f152dd0e9085a8d05fba9fb4b (diff) | |
ENGR00173586-2 [MX6] Add support to source GPT from 24MHz
On MX6Q TO1.1, MX6DL/S and MX6Solo, GPT can be sourced
from a constant source (better for frequency scaling).
Currently we set the GPT clock to 3MHz (24MHz div by 8).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock.c')
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 6c452c5cada9..746552759477 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -1732,15 +1732,31 @@ static struct clk vdoa_clk = { .disable = _clk_disable, }; +static unsigned long _clk_gpt_get_rate(struct clk *clk) +{ + u32 reg; + unsigned long rate; + + if (mx6q_revision() == IMX_CHIP_REVISION_1_0) + return clk_get_rate(clk->parent); + + rate = mx6_timer_rate(); + if (!rate) + return clk_get_rate(clk->parent); + + return rate; +} + static struct clk gpt_clk[] = { { __INIT_CLK_DEBUG(gpt_clk) - .parent = &ipg_perclk, + .parent = &osc_clk, .id = 0, .enable_reg = MXC_CCM_CCGR1, .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, .enable = _clk_enable, .disable = _clk_disable, + .get_rate = _clk_gpt_get_rate, .secondary = &gpt_clk[1], }, { @@ -5185,6 +5201,11 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* S/PDIF */ clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M); + if (mx6q_revision() == IMX_CHIP_REVISION_1_0) { + gpt_clk[0].parent = &ipg_perclk; + gpt_clk[0].get_rate = NULL; + } + base = ioremap(GPT_BASE_ADDR, SZ_4K); mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); |