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authorRanjani Vaidyanathan <ra5478@freescale.com>2012-04-17 23:05:43 -0500
committerJason Liu <r64343@freescale.com>2012-07-20 13:36:36 +0800
commite9ae3491d8266b484440ed564574e669bbe14a24 (patch)
tree3158862e9bcb3cc8c852b6decb020619cee50c90 /arch/arm/mach-mx6/clock.c
parent29105af181bfc3841ed4f9d09c7b8ca31f402dc6 (diff)
ENGR00180185: MX6-Add support for low power audio playback
The DDR frequency needs to be at 50MHz for low power audio playback. So added a new low power mode for audio. Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock.c')
-rw-r--r--arch/arm/mach-mx6/clock.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 259ebac1d5cd..7ee0f3e9c643 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -47,6 +47,7 @@ extern struct regulator *cpu_regulator;
extern struct cpu_op *(*get_cpu_op)(int *op);
extern int lp_high_freq;
extern int lp_med_freq;
+extern int lp_audio_freq;
void __iomem *apll_base;
static struct clk pll1_sys_main_clk;
@@ -2555,6 +2556,7 @@ static struct clk ssi1_clk = {
#else
.secondary = &mmdc_ch0_axi_clk[0],
#endif
+ .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE,
};
static unsigned long _clk_ssi2_get_rate(struct clk *clk)
@@ -2628,6 +2630,7 @@ static struct clk ssi2_clk = {
#else
.secondary = &mmdc_ch0_axi_clk[0],
#endif
+ .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE,
};
static unsigned long _clk_ssi3_get_rate(struct clk *clk)
@@ -2700,6 +2703,7 @@ static struct clk ssi3_clk = {
#else
.secondary = &mmdc_ch0_axi_clk[0],
#endif
+ .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE,
};
static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
@@ -5342,6 +5346,7 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
lp_high_freq = 0;
lp_med_freq = 0;
+ lp_audio_freq = 0;
/* Turn OFF all unnecessary PHYs. */
if (cpu_is_mx6q()) {