diff options
| author | Fugang Duan <B38611@freescale.com> | 2012-02-08 11:26:58 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:22:15 +0800 |
| commit | f8be5ffb1f330fe29bbaf009eac9bf2d0619dc25 (patch) | |
| tree | 9221dac31f3031de9a0502d87da5ccb166c6db54 /arch/arm/mach-mx6/clock.c | |
| parent | 32ac5f59d98764af99bb1bdf4f6fa2bfc8610327 (diff) | |
ENGR00172274-01 - [MX6]: rework IEEE-1588 ts_clk in MX6Q ARIK CPU board.
- Fix GPIO_16 IOMUX config.
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT.
- IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive,
because all of them use GPIO_16, so it only for one function
work at a moment.
- Test result:
Enet work fine at 100/1000Mbps in TO1.1.
IEEE 1588 timestamp is convergent.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock.c')
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 5adb3355f66c..c508b41d4730 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -3489,7 +3489,7 @@ static int _clk_enet_enable(struct clk *clk) /* Enable ENET ref clock */ reg = __raw_readl(PLL8_ENET_BASE_ADDR); reg &= ~ANADIG_PLL_BYPASS; - reg &= ~ANADIG_PLL_ENABLE; + reg |= ANADIG_PLL_ENABLE; __raw_writel(reg, PLL8_ENET_BASE_ADDR); _clk_enable(clk); @@ -3505,7 +3505,7 @@ static void _clk_enet_disable(struct clk *clk) /* Enable ENET ref clock */ reg = __raw_readl(PLL8_ENET_BASE_ADDR); reg |= ANADIG_PLL_BYPASS; - reg |= ANADIG_PLL_ENABLE; + reg &= ~ANADIG_PLL_ENABLE; __raw_writel(reg, PLL8_ENET_BASE_ADDR); } |