diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-07-27 16:41:58 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-07-30 20:13:33 -0500 |
| commit | 51e5dcf9e8b61a0af97852769c4b7ae1c01951d3 (patch) | |
| tree | 0003418ed696f7b0e61509b43cb930bcace2c2da /arch/arm/mach-mx6/cpu.c | |
| parent | ba0ad582e921bb4208b75289f3ecc22f773feb6e (diff) | |
ENGR00218747 - MX6Q/MX6DL: WAIT mode support for MX6QTO1.2/MX6DLTO1.1
Add the new WAIT mode workaround added for MX6Q1.2 and MX6DLTO1.1.
A new bit is added to CCM_CGPR (bit 17). This bit needs to be
enabled for the WAIT mode fix to be active and needs to be disabled
before the system enters STOP mode with power gating enabled.
Fix WAIT mode bug when system is in low power IDLE mode:
In low power IDLE mode (AHB @ 24MHz), switch ARM to run from 24MHz
on MX6QTO1.1 and MX6DLTO1.0 chips when ARM core enters WAIT mode.
We still need to use the ARM:IPG_CLK ratio of 12:5. Since IPG_CLK
is at 12MHz, we need to run ARM below 28.8MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/cpu.c')
| -rw-r--r-- | arch/arm/mach-mx6/cpu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c index 5d9749653988..9a60d9817ec3 100644 --- a/arch/arm/mach-mx6/cpu.c +++ b/arch/arm/mach-mx6/cpu.c @@ -35,6 +35,7 @@ struct cpu_op *(*get_cpu_op)(int *op); bool enable_wait_mode = true; u32 arm_max_freq = CPU_AT_1GHz; bool mem_clk_on_in_wait; +int chip_rev; void __iomem *gpc_base; void __iomem *ccm_base; @@ -197,6 +198,13 @@ static int __init post_cpu_init(void) (mx6dl_revision() < IMX_CHIP_REVISION_1_1)) mem_clk_on_in_wait = false; + if (cpu_is_mx6q()) + chip_rev = mx6q_revision(); + else if (cpu_is_mx6dl()) + chip_rev = mx6dl_revision; + else + chip_rev = mx6sl_revision; + return 0; } postcore_initcall(post_cpu_init); |