diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-12-12 12:42:58 -0600 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:19:03 +0800 |
| commit | ac9e30eacd35743ae1c24bccb82e247d9d4427ba (patch) | |
| tree | 40bdf4e885781c34a05fdb00f3cf61b0a116f605 /arch/arm/mach-mx6/cpu.c | |
| parent | 44d1c5e0aecad6e83df55816e641b7fb95ba1a5e (diff) | |
ENGR00170212: MX6 - Implement a SW workaround for TKT065875
Only CPU0 executes WFI followed by ISBs in uncached iRAM.
All other cores execute the regular cpu_do_idle()
This puts a restriction that all interrupts should only be routed to CPU0.
This bug should be fixed in TO1.1.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/cpu.c')
| -rw-r--r-- | arch/arm/mach-mx6/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c index bfc499328d4f..46e22f1138e4 100644 --- a/arch/arm/mach-mx6/cpu.c +++ b/arch/arm/mach-mx6/cpu.c @@ -33,7 +33,7 @@ void *mx6_wait_in_iram_base; -void (*mx6_wait_in_iram)(void *ccm_base); +void (*mx6_wait_in_iram)(); extern void mx6_wait(void); |