diff options
| author | Anson Huang <b20788@freescale.com> | 2013-01-21 16:20:56 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2013-01-28 10:18:51 +0800 |
| commit | c03a6de3bd70b3f99afa3ec532fbb7178819bfad (patch) | |
| tree | 12d54314c39f13f7b5a9969dd7dd4c36af36afa2 /arch/arm/mach-mx6/crm_regs.h | |
| parent | c27cb3851bb6f822f8a92e4a1e10fba19284bdd4 (diff) | |
ENGR00241003-1 mx6: need to add delay in LDO voltage setting
1.LDO ramp up time may be modified by ROM code
according to fuse setting, cpu freq driver use
fixed delay time which assume the LDO ramp up time
is the reset value of ANATOP register, need to set
it to reset value in regulator init.
2.The regulator set voltage should take care of
the ramp up time, calculate the ramp up time based
of register setting and to the delay, make sure that
when the set voltage function return, the voltage is
stable enough.
3.CPUFreq no need to use delay, it is already taken
care by regulator voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/crm_regs.h')
| -rw-r--r-- | arch/arm/mach-mx6/crm_regs.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h index 5e03312b7fce..43fcb4d0d466 100644 --- a/arch/arm/mach-mx6/crm_regs.h +++ b/arch/arm/mach-mx6/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -55,6 +55,7 @@ #define PFD_528_BASE_ADDR (MXC_PLL_BASE + 0x100) #define ANADIG_REG_CORE (MXC_PLL_BASE + 0x140) #define ANADIG_MISC1_REG (MXC_PLL_BASE + 0x160) +#define ANADIG_MISC2_REG (MXC_PLL_BASE + 0x170) #define ANATOP_LVDS_CLK1_SRC_SATA 0xB #define ANATOP_LVDS_CLK1_OBEN_MASK 0x400 #define ANATOP_LVDS_CLK1_IBEN_MASK 0x1000 @@ -154,6 +155,9 @@ #define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13) #define ANADIG_ANA_MISC2_CONTROL3_MASK 0xC0000000 #define ANADIG_ANA_MISC2_CONTROL3_OFFSET 30 +#define ANADIG_ANA_MISC2_REG0_STEP_TIME_MASK 0x30000000 +#define ANADIG_ANA_MISC2_REG1_STEP_TIME_MASK 0xC000000 +#define ANADIG_ANA_MISC2_REG2_STEP_TIME_MASK 0x3000000 #define MXC_CCM_BASE MX6_IO_ADDRESS(CCM_BASE_ADDR) /* CCM Register Offsets. */ |