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authorAnson Huang <b20788@freescale.com>2011-07-13 13:52:41 +0800
committerNitin Garg <nitin.garg@freescale.com>2014-06-03 19:29:57 -0500
commitae8c332e60dd580ca63785ef55d3921dc5995be3 (patch)
tree635a8a8a6d686a9eeaba870ba83342c40ed9126a /arch/arm/mach-mx6/mm.c
parent5c22940d8c86a62294c1331bfcc9d4deaadf2427 (diff)
ENGR00152668 [MX6]Enable arch_reset
--OCRAM size is 256KB, confirmed by IC owner, the OCRAM_Aliasd 0.75MB is mapped to the same 256KB OCRAM.That means there is only 256KB physical OCRAM. --Enable arch_reset function on MX6Q, For SMP, we need to clear the SRC_GPRx after the secondary cores brought up, or the wdog reset will fail; Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/mm.c')
-rw-r--r--arch/arm/mach-mx6/mm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/mm.c b/arch/arm/mach-mx6/mm.c
index 124144d61dce..ab91c38f433e 100644
--- a/arch/arm/mach-mx6/mm.c
+++ b/arch/arm/mach-mx6/mm.c
@@ -61,7 +61,7 @@ void __init mx6_map_io(void)
{
iotable_init(mx6_io_desc, ARRAY_SIZE(mx6_io_desc));
mxc_iomux_v3_init(IO_ADDRESS(MX6Q_IOMUXC_BASE_ADDR));
- mxc_arch_reset_init(IO_ADDRESS(WDOG1_BASE_ADDR));
+ mxc_arch_reset_init(IO_ADDRESS(MX6Q_WDOG1_BASE_ADDR));
}
#ifdef CONFIG_CACHE_L2X0
static int mxc_init_l2x0(void)