diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-12-12 12:42:58 -0600 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:19:03 +0800 |
| commit | ac9e30eacd35743ae1c24bccb82e247d9d4427ba (patch) | |
| tree | 40bdf4e885781c34a05fdb00f3cf61b0a116f605 /arch/arm/mach-mx6/system.c | |
| parent | 44d1c5e0aecad6e83df55816e641b7fb95ba1a5e (diff) | |
ENGR00170212: MX6 - Implement a SW workaround for TKT065875
Only CPU0 executes WFI followed by ISBs in uncached iRAM.
All other cores execute the regular cpu_do_idle()
This puts a restriction that all interrupts should only be routed to CPU0.
This bug should be fixed in TO1.1.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/system.c')
| -rw-r--r-- | arch/arm/mach-mx6/system.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 69e761c00402..8d8e0c747263 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -46,12 +46,13 @@ /* static DEFINE_SPINLOCK(wfi_lock); */ extern unsigned int gpc_wake_irq[4]; +extern int mx6q_revision(void); /* static unsigned int cpu_idle_mask; */ static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR); -extern void (*mx6_wait_in_iram)(void *ccm_base); +extern void (*mx6_wait_in_iram)(); extern void mx6_wait(void); extern void *mx6_wait_in_iram_base; extern bool enable_wait_mode; @@ -143,13 +144,17 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); } -void arch_idle(void) + void arch_idle(void) { if (enable_wait_mode) { if ((num_online_cpus() == num_present_cpus()) && mx6_wait_in_iram != NULL) { mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); - mx6_wait_in_iram(MXC_CCM_BASE); + if (smp_processor_id() == 0 && + (mx6q_revision() <= IMX_CHIP_REVISION_1_0)) + mx6_wait_in_iram(); + else + cpu_do_idle(); } } else cpu_do_idle(); |