ENGR00220153 cpufreq mx6: new cpu set point and add VDDSOC/PU adjust

1.add new cpu setpoint: replace 498Mhz with 672Mhz,and remove 198Mhz.
  but now 498Mhz seems not stable enough, comment now, test enough to
  add it. Rigel kept unchange now.
2.support adjusting VDDSOC/VDDPU when cpu frequency change.

Signed-off-by: Robin Gong <b38343@freescale.com>

9 files changed, 138 insertions, 46 deletions

diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c
index 4808272b9126..62db4d47ba41 100644
--- a/arch/arm/mach-mx6/board-mx6q_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6q_arm2.c
@@ -170,6 +170,8 @@ static int disable_mipi_dsi;
 extern struct regulator *(*get_cpu_regulator)(void);
 extern void (*put_cpu_regulator)(void);
 extern char *gp_reg_id;
+extern char *soc_reg_id;
+extern char *pu_reg_id;
 extern int epdc_enabled;
 extern void mx6_cpu_regulator_init(void);
 static int max17135_regulator_init(struct max17135 *max17135);
@@ -1893,6 +1895,8 @@ static struct mxc_mlb_platform_data mx6_arm2_mlb150_data = {
 
 static struct mxc_dvfs_platform_data arm2_dvfscore_data = {
 	.reg_id			= "cpu_vddgp",
+	.soc_id			= "cpu_vddsoc",
+	.pu_id			= "cpu_vddvpu",
 	.clk1_id		= "cpu_clk",
 	.clk2_id		= "gpc_dvfs_clk",
 	.gpc_cntr_offset	= MXC_GPC_CNTR_OFFSET,
@@ -2087,6 +2091,8 @@ static void __init mx6_arm2_init(void)
 	 */
 
 	gp_reg_id = arm2_dvfscore_data.reg_id;
+	soc_reg_id = arm2_dvfscore_data.soc_id;
+	pu_reg_id = arm2_dvfscore_data.pu_id;
 	mx6_arm2_init_uart();
 
 
diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
index cf146e032b58..6db0df13ec68 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
@@ -137,6 +137,10 @@
 #define SABREAUTO_USB_OTG_PWR		SABREAUTO_IO_EXP_GPIO3(1)
 #define BMCR_PDOWN			0x0800 /* PHY Powerdown */
 
+extern char *gp_reg_id;
+extern char *soc_reg_id;
+extern char *pu_reg_id;
+
 static int mma8451_position = 3;
 static struct clk *sata_clk;
 static int mipi_sensor;
@@ -1268,6 +1272,8 @@ static struct mxc_mlb_platform_data mx6_sabreauto_mlb150_data = {
 
 static struct mxc_dvfs_platform_data sabreauto_dvfscore_data = {
 	.reg_id			= "cpu_vddgp",
+	.soc_id			= "cpu_vddsoc",
+	.pu_id			= "cpu_vddvpu",
 	.clk1_id		= "cpu_clk",
 	.clk2_id 		= "gpc_dvfs_clk",
 	.gpc_cntr_offset 	= MXC_GPC_CNTR_OFFSET,
@@ -1491,6 +1497,8 @@ static void __init mx6_board_init(void)
 	}
 
 	gp_reg_id = sabreauto_dvfscore_data.reg_id;
+	soc_reg_id = sabreauto_dvfscore_data.soc_id;
+	pu_reg_id = sabreauto_dvfscore_data.pu_id;
 	mx6q_sabreauto_init_uart();
 	imx6q_add_mipi_csi2(&mipi_csi2_pdata);
 	if (cpu_is_mx6dl()) {
diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
index cd7298e6af06..d972cda66750 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
@@ -102,6 +102,8 @@ void __init early_console_setup(unsigned long base, struct clk *clk);
 static struct clk *sata_clk;
 
 extern char *gp_reg_id;
+extern char *soc_reg_id;
+extern char *pu_reg_id;
 
 extern struct regulator *(*get_cpu_regulator)(void);
 extern void (*put_cpu_regulator)(void);
@@ -1078,6 +1080,8 @@ static struct platform_pwm_backlight_data mx6_sabrelite_pwm_backlight_data = {
 
 static struct mxc_dvfs_platform_data sabrelite_dvfscore_data = {
 	.reg_id = "cpu_vddgp",
+	.soc_id = "cpu_vddsoc",
+	.pu_id = "cpu_vddvpu",
 	.clk1_id = "cpu_clk",
 	.clk2_id = "gpc_dvfs_clk",
 	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
@@ -1158,6 +1162,8 @@ static void __init mx6_sabrelite_board_init(void)
 #endif
 
 	gp_reg_id = sabrelite_dvfscore_data.reg_id;
+	soc_reg_id = sabrelite_dvfscore_data.soc_id;
+	pu_reg_id = sabrelite_dvfscore_data.pu_id;
 	mx6q_sabrelite_init_uart();
 	imx6q_add_mxc_hdmi_core(&hdmi_core_data);
 
diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c
index 68783725b686..eb0f8fc6fb1e 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabresd.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c
@@ -208,6 +208,8 @@ static int enable_lcd_ldb;
 
 
 extern char *gp_reg_id;
+extern char *soc_reg_id;
+extern char *pu_reg_id;
 extern int epdc_enabled;
 
 static int max17135_regulator_init(struct max17135 *max17135);
@@ -1595,6 +1597,8 @@ static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
 	.reg_id = "VDDCORE",
 	#else
 	.reg_id = "cpu_vddgp",
+	.soc_id = "cpu_vddsoc",
+	.pu_id = "cpu_vddvpu",
 	#endif
 	.clk1_id = "cpu_clk",
 	.clk2_id = "gpc_dvfs_clk",
@@ -1706,6 +1710,8 @@ static void __init mx6_sabresd_board_init(void)
 #endif
 
 	gp_reg_id = sabresd_dvfscore_data.reg_id;
+	soc_reg_id = sabresd_dvfscore_data.soc_id;
+	pu_reg_id = sabresd_dvfscore_data.pu_id;
 	mx6q_sabresd_init_uart();
 
 	/*
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c
index 0097fdc05fa7..249912b82d04 100755
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c
@@ -133,6 +133,9 @@ static int spdc_sel;
 static int max17135_regulator_init(struct max17135 *max17135);
 struct clk *extern_audio_root;
 
+extern char *gp_reg_id;
+extern char *soc_reg_id;
+extern char *pu_reg_id;
 extern int __init mx6sl_arm2_init_pfuze100(u32 int_gpio);
 
 enum sd_pad_mode {
@@ -632,7 +635,13 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
 };
 
 static struct mxc_dvfs_platform_data mx6sl_arm2_dvfscore_data = {
+	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	.reg_id			= "VDDCORE",
+	#else
 	.reg_id			= "cpu_vddgp",
+	.soc_id			= "cpu_vddsoc",
+	.pu_id			= "cpu_vddvpu",
+	#endif
 	.clk1_id		= "cpu_clk",
 	.clk2_id		= "gpc_dvfs_clk",
 	.gpc_cntr_offset	= MXC_GPC_CNTR_OFFSET,
@@ -1228,9 +1237,11 @@ static void __init mx6_arm2_init(void)
 	elan_ts_init();
 
 	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
-	gp_reg_id = "VDDCORE";
+	gp_reg_id = mx6sl_arm2_dvfscore_data.reg_id;
 	#else
-	gp_reg_id = "cpu_vddgp";
+	gp_reg_id = mx6sl_arm2_dvfscore_data.reg_id;
+	soc_reg_id = mx6sl_arm2_dvfscore_data.soc_id;
+	pu_reg_id = mx6sl_arm2_dvfscore_data.pu_id;
 	mx6_cpu_regulator_init();
 	#endif
 
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index f21fab4bbe95..9731b3dc6f96 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -1272,6 +1272,11 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 				else
 					pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
 			}
+			if (cpu_op_tbl[i].cpu_podf) {
+				__raw_writel(cpu_op_tbl[i].cpu_podf, MXC_CCM_CACRR);
+				while (__raw_readl(MXC_CCM_CDHIPR))
+							;
+			}
 			pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
 		}
 		/* Make sure pll1_sw_clk is from pll1_sys_main_clk */
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 887e6ad6fa96..6e0bcc479585 100755
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -1159,6 +1159,11 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 				else
 					pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
 			}
+			if (cpu_op_tbl[i].cpu_podf) {
+				__raw_writel(cpu_op_tbl[i].cpu_podf, MXC_CCM_CACRR);
+				while (__raw_readl(MXC_CCM_CDHIPR))
+							;
+			}
 			pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
 		}
 		pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
diff --git a/arch/arm/mach-mx6/cpu_op-mx6.c b/arch/arm/mach-mx6/cpu_op-mx6.c
index 6fe2fd8e7cbb..98181ceb3670 100644
--- a/arch/arm/mach-mx6/cpu_op-mx6.c
+++ b/arch/arm/mach-mx6/cpu_op-mx6.c
@@ -23,60 +23,68 @@ extern void (*set_num_cpu_op)(int num);
 extern u32 arm_max_freq;
 static int num_cpu_op;
 
-/* working point(wp): 0 - 1.2GHz; 1 - 800MHz, 2 - 624MHz 3 - 400MHz, 4  - 200MHz */
+/* working point(wp): 0 - 1.2GHz; 1 - 792MHz, 2 - 498MHz 3 - 396MHz */
 static struct cpu_op mx6_cpu_op_1_2G[] = {
 	{
 	 .pll_rate = 1200000000,
 	 .cpu_rate = 1200000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1250000,
+	 .soc_voltage = 1250000,
 	 .cpu_voltage = 1275000,},
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
 	 .cpu_voltage = 1100000,},
-	{
-	 .pll_rate = 672000000,
-	 .cpu_rate = 672000000,
-	 .cpu_voltage = 1050000,},
+/*	{
+	 .pll_rate = 996000000,
+	 .cpu_rate = 498000000,
+	 .cpu_podf = 1,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
+	 .cpu_voltage = 1050000,},*/
 	 {
 	  .pll_rate = 396000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	  .cpu_voltage = 950000,},
-	{
-	 .pll_rate = 396000000,
-	 .cpu_rate = 198000000,
-	 .cpu_podf = 1,
-	 .cpu_voltage = 850000,},
+	  .pu_voltage = 1100000,
+	  .soc_voltage = 1100000,
+	  .cpu_voltage = 925000,},
 };
 
-/* working point(wp): 0 - 1GHz; 1 - 800MHz, 2 - 624MHz 3 - 400MHz, 4  - 200MHz */
+/* working point(wp): 0 - 1GHz; 1 - 792MHz, 2 - 498MHz 3 - 396MHz */
 static struct cpu_op mx6_cpu_op_1G[] = {
 	{
 	 .pll_rate = 996000000,
 	 .cpu_rate = 996000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1200000,
+	 .soc_voltage = 1200000,
 	 .cpu_voltage = 1225000,},
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
 	 .cpu_voltage = 1100000,},
-	{
-	 .pll_rate = 672000000,
-	 .cpu_rate = 672000000,
-	 .cpu_voltage = 1050000,},
+/*	{
+	 .pll_rate = 996000000,
+	 .cpu_rate = 498000000,
+	 .cpu_podf = 1,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
+	 .cpu_voltage = 1050000,},*/
 	 {
 	  .pll_rate = 396000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	  .cpu_voltage = 950000,},
-	{
-	 .pll_rate = 396000000,
-	 .cpu_rate = 198000000,
-	 .cpu_podf = 1,
-	 .cpu_voltage = 850000,},
+	  .pu_voltage = 1100000,
+	  .soc_voltage = 1100000,
+	  .cpu_voltage = 925000,},
 };
 
 static struct cpu_op mx6_cpu_op[] = {
@@ -84,17 +92,23 @@ static struct cpu_op mx6_cpu_op[] = {
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
 	 .cpu_voltage = 1100000,},
+/*	{
+	 .pll_rate = 996000000,
+	 .cpu_rate = 498000000,
+	 .cpu_podf = 1,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
+	 .cpu_voltage = 1050000,},*/
 	 {
 	  .pll_rate = 396000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	  .cpu_voltage = 950000,},
-	{
-	 .pll_rate = 396000000,
-	 .cpu_rate = 198000000,
-	 .cpu_podf = 1,
-	 .cpu_voltage = 850000,},
+	  .pu_voltage = 1100000,
+	  .soc_voltage = 1100000,
+	  .cpu_voltage = 925000,},
 };
 
 /* working point(wp): 0 - 1.2GHz; 1 - 800MHz, 2 - 400MHz, 3  - 200MHz */
@@ -103,22 +117,30 @@ static struct cpu_op mx6dl_cpu_op_1_2G[] = {
 	 .pll_rate = 1200000000,
 	 .cpu_rate = 1200000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1250000,
+	 .soc_voltage = 1250000,
 	 .cpu_voltage = 1275000,},
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
-	 .cpu_voltage = 1100000,},
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
+	 .cpu_voltage = 1125000,},
 	 {
 	  .pll_rate = 396000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	  .cpu_voltage = 1000000,},
-	{
-	 .pll_rate = 396000000,
-	 .cpu_rate = 198000000,
-	 .cpu_podf = 1,
-	 .cpu_voltage = 1000000,},
+	  .pu_voltage = 1100000,
+	  .soc_voltage = 1100000,
+	  .cpu_voltage = 1025000,},
+	 {
+	  .pll_rate = 396000000,
+	  .cpu_rate = 198000000,
+	  .cpu_podf = 1,
+	  .pu_voltage = 1100000,
+	  .soc_voltage = 1100000,
+	  .cpu_voltage = 1025000,},
 };
 /* working point(wp): 0 - 1GHz; 1 - 800MHz, 2 - 400MHz, 3  - 200MHz */
 static struct cpu_op mx6dl_cpu_op_1G[] = {
@@ -126,39 +148,52 @@ static struct cpu_op mx6dl_cpu_op_1G[] = {
 	 .pll_rate = 996000000,
 	 .cpu_rate = 996000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1200000,
+	 .soc_voltage = 1200000,
 	 .cpu_voltage = 1225000,},
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
 	 .cpu_voltage = 1125000,},
-	 {
-	  .pll_rate = 396000000,
-	  .cpu_rate = 396000000,
-	  .cpu_podf = 0,
-	  .cpu_voltage = 1025000,},
 	{
 	 .pll_rate = 396000000,
-	 .cpu_rate = 198000000,
-	 .cpu_podf = 1,
+	 .cpu_rate = 396000000,
+	 .cpu_podf = 0,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
 	 .cpu_voltage = 1025000,},
+	 {
+	  .pll_rate = 396000000,
+	  .cpu_rate = 198000000,
+	  .cpu_podf = 1,
+	  .pu_voltage = 1100000,
+	  .soc_voltage = 1100000,
+	  .cpu_voltage = 1025000,},
 };
-
 static struct cpu_op mx6dl_cpu_op[] = {
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
 	 .cpu_voltage = 1100000,},
 	 {
 	  .pll_rate = 396000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
+	  .pu_voltage = 1100000,
+	  .soc_voltage = 1100000,
 	  .cpu_voltage = 1000000,},
 	{
 	 .pll_rate = 396000000,
 	 .cpu_rate = 198000000,
 	 .cpu_podf = 1,
+	 .pu_voltage = 1100000,
+	 .soc_voltage = 1100000,
 	 .cpu_voltage = 1000000,},
 };
 
diff --git a/arch/arm/mach-mx6/cpu_regulator-mx6.c b/arch/arm/mach-mx6/cpu_regulator-mx6.c
index 779ed62eea53..cb08cad48204 100644
--- a/arch/arm/mach-mx6/cpu_regulator-mx6.c
+++ b/arch/arm/mach-mx6/cpu_regulator-mx6.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -26,7 +26,11 @@
 #include <mach/hardware.h>
 
 struct regulator *cpu_regulator;
+struct regulator *soc_regulator;
+struct regulator *pu_regulator;
 char *gp_reg_id;
+char *soc_reg_id;
+char *pu_reg_id;
 static struct clk *cpu_clk;
 static int cpu_op_nr;
 static struct cpu_op *cpu_op_tbl;
@@ -98,5 +102,11 @@ void mx6_cpu_regulator_init(void)
 #endif
 		}
 	}
+	soc_regulator = regulator_get(NULL, soc_reg_id);
+	if (IS_ERR(soc_regulator))
+		printk(KERN_ERR "%s: failed to get soc regulator\n", __func__);
+	pu_regulator = regulator_get(NULL, pu_reg_id);
+	if (IS_ERR(pu_regulator))
+		printk(KERN_ERR "%s: failed to get pu regulator\n", __func__);
 }