diff options
author | Gary Zhang <b13634@freescale.com> | 2012-03-01 16:09:18 +0800 |
---|---|---|
committer | Gary Zhang <b13634@freescale.com> | 2012-03-02 15:44:07 +0800 |
commit | 12027b4c9cda17411ac41d29e24a53743c407b4d (patch) | |
tree | 52b7e13c67122cebee531fbe5e6825558da53ba9 /arch/arm/mach-mx6 | |
parent | c9b68a017d4c409ca3ba7e61d0caa858b8fee372 (diff) |
ENGR00175219-5 MX6: remove cko1_clk in clock.c
there are clko_clk and cko1_clk in clock.c which operate
the same CKO1 clock source.
remove cko1_clk codes to avoid operation confusion.
Signed-off-by: Gary Zhang <b13634@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6')
-rw-r--r-- | arch/arm/mach-mx6/clock.c | 125 |
1 files changed, 1 insertions, 124 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 17251f9ac709..169bbbef750a 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -60,8 +60,6 @@ static struct clk pll8_enet_main_clk; static struct clk apbh_dma_clk; static struct clk openvg_axi_clk; static struct clk enfc_clk; -static struct clk ipu1_di_clk_root; -static struct clk ipu2_di_clk_root; static struct clk usdhc3_clk; static struct cpu_op *cpu_op_tbl; @@ -2077,123 +2075,6 @@ static struct clk ipu1_clk = { .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; -static int _clk_cko1_clk0_set_parent(struct clk *clk, struct clk *parent) -{ - u32 sel, reg; - - if (parent == &pll3_sw_clk) - sel = 0; - else if (parent == &pll2_528_bus_main_clk) - sel = 1; - else if (parent == &pll1_sys_main_clk) - sel = 2; - else if (parent == &pll5_video_main_clk) - sel = 3; - else if (parent == &axi_clk) - sel = 5; - else if (parent == &enfc_clk) - sel = 6; - else if (parent == &ipu1_di_clk_root) - sel = 7; - else if (parent == &ipu1_di_clk_root) - sel = 8; - else if (parent == &ipu2_di_clk_root) - sel = 9; - else if (parent == &ipu2_di_clk_root) - sel = 10; - else if (parent == &ahb_clk) - sel = 11; - else if (parent == &ipg_clk) - sel = 12; - else if (parent == &ipg_perclk) - sel = 13; - else if (parent == &ckil_clk) - sel = 14; - else if (parent == &pll4_audio_main_clk) - sel = 15; - else - return -EINVAL; - - reg = __raw_readl(MXC_CCM_CCOSR); - reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK; - reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET; - __raw_writel(reg, MXC_CCM_CCOSR); - return 0; -} - -static unsigned long _clk_cko1_round_rate(struct clk *clk, - unsigned long rate) -{ - u32 div; - u32 parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - - /* Make sure rate is not greater than the maximum value for the clock. - * Also prevent a div of 0. - */ - if (div == 0) - div++; - - if (div > 8) - div = 8; - - return parent_rate / div; -} - -static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg, div; - u32 parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (div == 0) - div++; - if (((parent_rate / div) != rate) || (div > 8)) - return -EINVAL; - - reg = __raw_readl(MXC_CCM_CCOSR); - reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK; - reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET; - __raw_writel(reg, MXC_CCM_CCOSR); - - return 0; -} - -static unsigned long _clk_cko1_get_rate(struct clk *clk) -{ - u32 reg, div; - - reg = __raw_readl(MXC_CCM_CCOSR); - div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >> - MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1; - - return clk_get_rate(clk->parent) / div; -} - -static int cko1_clk_enable(struct clk *clk) -{ - u32 reg; - reg = __raw_readl(clk->enable_reg); - reg |= clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - - return 0; -} - -static struct clk cko1_clk0 = { - __INIT_CLK_DEBUG(cko1_clk0) - .parent = &ipg_clk, - .enable_reg = MXC_CCM_CCOSR, - .enable_shift = MXC_CCM_CCOSR_CKOL_EN, - .enable = cko1_clk_enable, - .disable = _clk_disable, - .set_parent = _clk_cko1_clk0_set_parent, - .round_rate = _clk_cko1_round_rate, - .set_rate = _clk_cko1_set_rate, - .get_rate = _clk_cko1_get_rate, -}; - static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent) { int mux; @@ -5130,7 +5011,6 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]), _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk), _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk), - _REGISTER_CLOCK(NULL, "cko1_clk0", cko1_clk0), _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk), _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk), _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk), @@ -5280,10 +5160,6 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk); clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk); - clk_set_parent(&cko1_clk0, &ipg_clk); - clk_set_rate(&cko1_clk0, 22000000); - clk_enable(&cko1_clk0); - clk_set_parent(&emi_clk, &pll2_pfd_400M); clk_set_rate(&emi_clk, 200000000); @@ -5315,6 +5191,7 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, clk_set_parent(&clko2_clk, &osc_clk); clk_set_rate(&clko2_clk, 2400000); + clk_set_parent(&clko_clk, &ipg_clk); /* * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample * rate convertion and this clock frequency can not be too high, set |