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authorTero Kristo <t-kristo@ti.com>2014-07-02 11:47:42 +0300
committerPaul Walmsley <paul@pwsan.com>2014-07-15 14:09:06 -0600
commit512d91cbd990c67df16d0a7b3ff5d35055ac6b39 (patch)
treed9ebd1366f12859ab6184ffe8595c2649f186cff /arch/arm/mach-omap2/clock.c
parent5f84aeb6a194ed127d1beb61738577c15a60172b (diff)
ARM: OMAP2+: clock/dpll: convert bypass check to use clk_features
OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses clk_features data provided during boot. This avoids the need to use cpu_is_X type checks runtime, and allows us to eventually move the clock code under the clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
-rw-r--r--arch/arm/mach-omap2/clock.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 7efe66e3a029..e4384377d9f8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -767,4 +767,21 @@ void __init ti_clk_init_features(void)
ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
}
+
+ /* Bypass value setup for DPLLs */
+ if (cpu_is_omap24xx()) {
+ ti_clk_features.dpll_bypass_vals |=
+ (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
+ (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
+ } else if (cpu_is_omap34xx()) {
+ ti_clk_features.dpll_bypass_vals |=
+ (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
+ (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
+ } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
+ soc_is_omap54xx() || soc_is_dra7xx()) {
+ ti_clk_features.dpll_bypass_vals |=
+ (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
+ (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
+ (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
+ }
}