diff options
| author | Paul Walmsley <paul@pwsan.com> | 2010-01-26 20:13:11 -0700 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2010-01-29 10:14:22 -0700 |
| commit | feec1277a5c599ebca6217bc6bb9f6410e84793b (patch) | |
| tree | cd095939bdd63b102b235857d434c1890aba8450 /arch/arm/mach-omap2/clock34xx.c | |
| parent | da4d2904abc0c31ac829e9c6d52106d5a6606507 (diff) | |
OMAP2/3/4 clock: omap2_clk_prepare_for_reboot() is OMAP2xxx-only
omap2_clk_prepare_for_reboot() is only applicable to OMAP2xxx chips,
so rename it to omap2xxx_clk_prepare_for_reboot() and only call it when
running on OMAP2xxx chips. Remove the old stub in the OMAP3 clock code.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 21 |
1 files changed, 2 insertions, 19 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 8a7db7a03bec..34d395046280 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -150,25 +150,6 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) return omap3_noncore_dpll_set_rate(clk, rate); } -/* Common clock code */ - -/* - * Set clocks for bypass mode for reboot to work. - */ -void omap2_clk_prepare_for_reboot(void) -{ - /* REVISIT: Not ready for 343x */ -#if 0 - u32 rate; - - if (vclk == NULL || sclk == NULL) - return; - - rate = clk_get_rate(sclk); - clk_set_rate(vclk, rate); -#endif -} - void omap3_clk_lock_dpll5(void) { struct clk *dpll5_clk; @@ -191,6 +172,8 @@ void omap3_clk_lock_dpll5(void) return; } +/* Common clock code */ + /* REVISIT: Move this init stuff out into clock.c */ /* |