diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2012-03-19 19:29:41 +0530 |
|---|---|---|
| committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2012-07-09 19:14:39 +0530 |
| commit | 283f708ca846903ee045e9f9374d627f7b47a711 (patch) | |
| tree | cfd5db40a28e4c02ed0696fbd63945157e73020d /arch/arm/mach-omap2/omap-headsmp.S | |
| parent | 247c445c0fbd52c77e497ff5bfcf0dceb8afea8d (diff) | |
ARM: OMAP5: Add SMP support
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap-headsmp.S')
| -rw-r--r-- | arch/arm/mach-omap2/omap-headsmp.S | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 503ac777a2ba..502e3135aad3 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -19,6 +19,27 @@ #include <linux/init.h> __CPUINIT + +/* Physical address needed since MMU not enabled yet on secondary core */ +#define AUX_CORE_BOOT0_PA 0x48281800 + +/* + * OMAP5 specific entry point for secondary CPU to jump from ROM + * code. This routine also provides a holding flag into which + * secondary core is held until we're ready for it to initialise. + * The primary core will update this flag using a hardware ++ * register AuxCoreBoot0. + */ +ENTRY(omap5_secondary_startup) +wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 + ldr r0, [r2] + mov r0, r0, lsr #5 + mrc p15, 0, r4, c0, c0, 5 + and r4, r4, #0x0f + cmp r0, r4 + bne wait + b secondary_startup +END(omap5_secondary_startup) /* * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which |