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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-16 17:45:56 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-30 00:49:36 +0100
commit36827edd2e3711749ff472949b9cf94f4cb700e9 (patch)
treee259a7ba35638ae7fea8a95f9e2fc23c4da794cf /arch/arm/mach-omap2/omap4-common.c
parent8523f615377f661dac7a784193fa842d45dd3fd9 (diff)
ARM: l2c: omap2: implement new write_sec method
With the write_sec method, we no longer need to override the default L2C disable method, and we no longer need the L2C set_debug method. Both of these can be handled via the write_sec method. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/omap4-common.c')
-rw-r--r--arch/arm/mach-omap2/omap4-common.c42
1 files changed, 26 insertions, 16 deletions
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index fb149b03d56d..44472b7469c5 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -167,17 +167,33 @@ void __iomem *omap4_get_l2cache_base(void)
return l2cache_base;
}
-static void omap4_l2x0_disable(void)
+static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
{
- outer_flush_all();
- /* Disable PL310 L2 Cache controller */
- omap_smc1(0x102, 0x0);
-}
+ unsigned smc_op;
-static void omap4_l2x0_set_debug(unsigned long val)
-{
- /* Program PL310 L2 Cache controller debug register */
- omap_smc1(0x100, val);
+ switch (reg) {
+ case L2X0_CTRL:
+ smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
+ break;
+
+ case L2X0_AUX_CTRL:
+ smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
+ break;
+
+ case L2X0_DEBUG_CTRL:
+ smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
+ break;
+
+ case L310_PREFETCH_CTRL:
+ smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
+ break;
+
+ default:
+ WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
+ return;
+ }
+
+ omap_smc1(smc_op, val);
}
static int __init omap_l2_cache_init(void)
@@ -211,18 +227,12 @@ static int __init omap_l2_cache_init(void)
/* Enable PL310 L2 Cache controller */
omap_smc1(0x102, 0x1);
+ outer_cache.write_sec = omap4_l2c310_write_sec;
if (of_have_populated_dt())
l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
else
l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
- /*
- * Override default outer_cache.disable with a OMAP4
- * specific one
- */
- outer_cache.disable = omap4_l2x0_disable;
- outer_cache.set_debug = omap4_l2x0_set_debug;
-
return 0;
}
omap_early_initcall(omap_l2_cache_init);