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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 22:57:33 -0300
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 11:26:23 -0300
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /arch/arm/mach-pxa
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/arm/mach-pxa')
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/zeus.h2
-rw-r--r--arch/arm/mach-pxa/mioa701.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index e4fb4668c26e..207ecb49a61b 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -38,7 +38,7 @@
#define PCMD(x) __REG(0x40F50110 + ((x) << 2))
/*
- * Slave Power Managment Unit
+ * Slave Power Management Unit
*/
#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
index faa408ab7ad7..0641f31a56b7 100644
--- a/arch/arm/mach-pxa/include/mach/zeus.h
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -64,7 +64,7 @@
/*
* CPLD registers:
- * Only 4 registers, but spreaded over a 32MB address space.
+ * Only 4 registers, but spread over a 32MB address space.
* Be gentle, and remap that over 32kB...
*/
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dd13bb63259b..23925db8ff74 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -458,7 +458,7 @@ static struct platform_device strataflash = {
/*
* Suspend/Resume bootstrap management
*
- * MIO A701 reboot sequence is highly ROM dependant. From the one dissassembled,
+ * MIO A701 reboot sequence is highly ROM dependent. From the one dissassembled,
* this sequence is as follows :
* - disables interrupts
* - initialize SDRAM (self refresh RAM into active RAM)